Explicit Codes Uniformly Reducing Repair Bandwidth in Distributed Storage

A distributed storage setting is considered where a file of size B is to be stored across n storage nodes. A data collector should be able to reconstruct the entire data by downloading the symbols stored in any k nodes. When a node fails, it is replaced by a new node by downloading data from some of the existing nodes. The amount of download is termed as repair bandwidth. One way to implement such a system is to store one fragment of an (n, k) MDS code in each node, in which case the repair bandwidth is B. Since repair of a failed node consumes network bandwidth, codes reducing repair bandwidth are of great interest. Most of the recent work in this area focuses on reducing the repair bandwidth of a set of k nodes which store the data in uncoded form, while the reduction in the repair bandwidth of the remaining nodes is only marginal. In this paper, we present an explicit code which reduces the repair bandwidth for all the nodes to approximately B/2. To the best of our knowledge, this is the first explicit code which reduces the repair bandwidth of all the nodes for all feasible values of the system parameters.

A Nonlinear Voltage Regulator With One Tunable Parameter for Multimachine Power Systems

This paper proposes a nonlinear voltage regulator with one tunable parameter for multimachine power systems. Based on output feedback linearization, this regulator can achieve simultaneous voltage regulation and small-signal performance objectives. Conventionally output feedback linearization has been used for voltage regulator design by taking infinite bus voltage as reference. Unfortunately, this controller has poor small-signal performance and cannot be applied to multimachine systems without the estimation of the equivalent external reactance seen from the generator. This paper proposes a voltage regulator design by redefining the rotor angle at each generator with respect to the secondary voltage of the step-up transformer as reference instead of a common synchronously rotating reference frame. Using synchronizing and damping torques analysis, we show that the proposed voltage regulator achieves simultaneous voltage regulation and damping performance over a range of system and operating conditions by controlling the relative angle between the generator internal voltage angle delta and the secondary voltage of the step up transformer. The performance of the proposed voltage regulator is evaluated on a single machine infinite bus system and two widely used multimachine test systems.

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

Simulation Blocks for TOSSIM-T2"

We develop several hardware and software simulation blocks for the TinyOS-2 (TOSSIM-T2) simulator. The choice of simulated hardware platform is the popular MICA2 mote. While the hardware simulation elements comprise of radio and external flash memory, the software blocks include an environment noise model, packet delivery model and an energy estimator block for the complete system. The hardware radio block uses the software environment noise model to sample the noise floor.The packet delivery model is built by establishing the SNR-PRR curve for the MICA2 system. The energy estimator block models energy consumption by Micro Controller Unit(MCU), Radio,LEDs, and external flash memory. Using the manufacturer’s data sheets we provide an estimate of the energy consumed by the hardware during transmission, reception and also track several of the MCUs states with the associated energy consumption. To study the effectiveness of this work, we take a case study of a paper presented in [1]. We obtain three sets of results for energy consumption through mathematical analysis, simulation using the blocks built into PowerTossim-T2 and finally laboratory measurements. Since there is a significant match between these result sets, we propose our blocks for T2 community to effectively test their application energy requirements and node life times.

A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.