Static Balancing of Spring-loaded Planar Revolute-joint Linkages without Auxiliary Links

We present a method to statically balance a general treestructured,planar revolute-joint linkage loaded with linear springs or constant forces without using auxiliary links. The balancing methods currently documented in the literature use extra links; some do not apply when there are spring loads and some are restricted to only two-link serial chains. In our method, we suitably combine any non-zero-free-length load spring with another spring to result in an effective zero-free-length spring load. If a link has a single joint (with the parent link), we give a procedure to attach extra zero-free-length springs to it so that forces and moments are balanced for the link. Another consequence of this attachment is that the constraint force of the joint on the parent link becomes equivalent to a zero-free-length spring load. Hence, conceptually,for the parent link, the joint with its child is removed and replaced with the zero-free-length spring. This feature allows recursive application of this procedure from the end-branches of the tree down to the root, satisfying force and moment balance of all the links in the process. Furthermore, this method can easily be extended to the closed-loop revolute-joint linkages, which is also illustrated in the paper.

Design and Implementation of a Flexible and Memory Efficient Operating System for Sensor Nodes

Sensor network nodes exhibit characteristics of both embedded systems and general-purpose systems.A sensor network operating system is a kind of embedded operating system, but unlike a typical embedded operating system, sensor network operatin g system may not be real time, and is constrained by memory and energy constraints. Most sensor network operating systems are based on event-driven approach. Event-driven approach is efficient in terms of time and space.Also this approach does not require a separate stack for each execution context. But using this model, it is difficult to implement long running tasks, like cryptographic operations. A thread based computation requires a separate stack for each execution context, and is less efficient in terms of time and space. In this paper, we propose a thread based execution model that uses only a fixed number of stacks. In this execution model, the number of stacks at each priority level are fixed. It minimizes the stack requirement for multi-threading environment and at the same time provides ease of programming. We give an implementation of this model in Contiki OS by separating thread implementation from protothread implementation completely. We have tested our OS by implementing a clock synchronization protocol using it.

Determining Top K Nodes in Social Networks using the Shapley Value

In this paper, we consider the problem of selecting, for any given positive integer k, the top-k nodes in a social network, based on a certain measure appropriate for the social network. This problem is relevant in many settings such as analysis of co-authorship networks, diffusion of information, viral marketing, etc. However, in most situations, this problem turns out to be NP-hard. The existing approaches for solving this problem are based on approximation algorithms and assume that the objective function is sub-modular. In this paper, we propose a novel and intuitive algorithm based on the Shapley value, for efficiently computing an approximate solution to this problem. Our proposed algorithm does not use the sub-modularity of the underlying objective function and hence it is a general approach. We demonstrate the efficacy of the algorithm using a co-authorship data set from e-print arXiv (www.arxiv.org), having 8361 authors.

Computationally Efficient Sub-optimal Mid Course Guidance Using Model Predictive Static Programming (MPSP)

For a homing interceptor, suitable initial condition must be achieved by mid course guidance scheme for its maximum effectiveness. To achieve desired end goal of any mid course guidance scheme, two point boundary value problem must be solved online with all realistic constrain. A Newly developed computationally efficient technique named as MPSP (Model Predictive Static Programming) is utilized in this paper for obtaining suboptimal solution of optimal mid course guidance. Time to go uncertainty is avoided in this formulation by making use of desired position where midcourse guidance terminate and terminal guidance takes over. A suitable approach angle towards desired point also can be specified in this guidance law formulation. This feature makes this law particularly attractive because warhead effectiveness issue can be indirectly solved in mid course phase.

Necessity for quatum simulation for future technology nodes

In this paper we present and compare the results obtained from semi-classical and quantum mechanical simulation for a double gate MOSFET structure to analyze the electrostatics and carrier dynamics of this device. The geometries like gate length, body thickness of this device have been chosen according to the ITRS specification for the different technology nodes. We have shown the extent of deviation between the semi- classical and quantum mechanical results and hence the need of quantum simulations for the promising nanoscale devices in the future technology nodes predicted in ITRS.

Process Variation Aware Estimation of Static Leakage Power in Nano-CMOS

We present a statistical methodology for leakage power estimation, due to subthreshold and gate tunneling leakage, in the presence of process variations, for 65 nm CMOS. The circuit leakage power variations is analyzed by Monte Carlo (MC) simulations, by characterizing NAND gate library. A statistical “hybrid model” is proposed, to extend this methodology to a generic library. We demonstrate that hybrid model based statistical design results in up to 95% improvement in the prediction of worst to best corner leakage spread, with an error of less than 0.5%, with respect to worst case design.

Broadcast in Adhoc Wireless Networks with Selfish Nodes: A Bayesian Incentive Compatibility Approach

We consider the incentive compatible broadcast (ICB) problem in ad hoc wireless networks with selfish nodes. We design a Bayesian incentive compatible broadcast (BIC-B) protocol to address this problem. VCG mechanism based schemes have been popularly used in the literature to design dominant strategy incentive compatible (DSIC) protocols for ad hoc wireless networks. VCG based mechanisms have two critical limitations: (i) the network is required to be bi-connected, (ii) the resulting protocol is not budget balanced. Our proposed BIC-B protocol overcomes these difficulties. We also prove the optimality of the proposed scheme.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes

We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.