Experimental characterisation and performance evaluation of a coaxial current transformer for measurement of insulated gate bipolar transistor switching current

Measurement of device current during switching characterisation of an insulated gate bipolar transistor (IGBT) requires a current sensor with low insertion impedance and high bandwidth. This study presents an experimental procedure for evaluating the performance of a coaxial current transformer (CCT), designed for the above purpose. A prototype CCT, which can be mounted directly on a power terminal of a 1200 V/50 A half-bridge IGBT module, is characterised experimentally. The measured characteristics include insertion impedance, gain and phase of the CCT at different frequencies. The bounds of linearity within which the CCT can operate without saturation are determined theoretically, and are also verified experimentally. The experimental study on linearity of the CCT requires a high-amplitude current source. A proportional-resonant (PR) controller-based current-controlled half-bridge inverter is developed for this purpose. A systematic procedure for selection of PR controller parameters is also reported in this study. This set-up is helpful to determine the limit of linearity and also to measure the frequency response of the CCT at realistic amplitudes of current in the low-frequency range.

Instability in an amorphous In-Ga-Zn-O field effect transistor upon water exposure

The instability of an amorphous indium-gallium-zinc oxide (IGZO) field effect transistor is investigated upon water treatment. Electrical characteristics are measured before, immediately after and a few days after water treatment in ambient as well as in vacuum conditions. It is observed that after a few days of water exposure an IGZO field effect transistor (FET) shows relatively more stable behaviour as compared to before exposure. Transfer characteristics are found to shift negatively after immediate water exposure and in vacuum. More interestingly, after water exposure the off current is found to decrease by 1-2 orders of magnitude and remains stable even after 15 d of water exposure in ambient as well as in vacuum, whereas the on current more or less remains the same. An x-ray photoelectron spectroscopic study is carried out to investigate the qualitative and quantitative analysis of IGZO upon water exposure. The changes in the FET parameters are evaluated and attributed to the formation of excess oxygen vacancies and changes in the electronic structure of the IGZO bulk channel and at the IGZO/SiO2 interface, which can further lead to the formation of subgap states. An attempt is made to distinguish which parameters of the FET are affected by the changes in the electronic structure of the IGZO bulk channel and at the IGZO/SiO2 interface separately.

Electron-hole asymmetry in the electron-phonon coupling in top-gated phosphorene transistor

Using in situ Raman scattering from phosphorene channel in an electrochemically top-gated field effect transistor, we show that phonons with A(g) symmetry depend much more strongly on concentration of electrons than that of holes, wheras phonons with B-g symmetry are insensitive to doping. With first-principles theoretical analysis, we show that the observed electon-hole asymmetry arises from the radically different constitution of its conduction and valence bands involving pi and sigma bonding states respectively, whose symmetry permits coupling with only the phonons that preserve the lattice symmetry. Thus, Raman spectroscopy is a non-invasive tool for measuring electron concentration in phosphorene-based nanoelectronic devices.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors

As the conventional MOSFET's scaling is approaching the limit imposed by short channel effects, Double Gate (DG) MOS transistors are appearing as the most feasible candidate in terms of technology in sub-45nm technology nodes. As the short channel effect in DG transistor is controlled by the device geometry, undoped or lightly doped body is used to sustain the channel. There exits a disparity in threshold voltage calculation criteria of undoped-body symmetric double gate transistors which uses two definitions, one is potential based and the another is charge based definition. In this paper, a novel concept of "crossover point'' is introduced, which proves that the charge-based definition is more accurate than the potential based definition.The change in threshold voltage with body thickness variation for a fixed channel length is anomalous as predicted by potential based definition while it is monotonous for charge based definition.The threshold voltage is then extracted from drain currant versus gate voltage characteristics using linear extrapolation and "Third Derivative of Drain-Source Current'' method or simply "TD'' method. The trend of threshold voltage variation is found same in both the cases which support charge-based definition.

Concept of Crossover point and its application on Threshold Voltage definition for Undoped-Body Transistors

As the conventional MOSFETs scaling is approaching the limit imposed by short channel effects, Double Gate (DG) MOS transistors are appearing as the most feasible andidate in terms of technology in sub-45nm technology nodes. As the short channel effect in DG transistor is controlled by the device geometry, undoped or lightly doped body, is used to sustain the channel. There exits a disparity in threshold voltage calculation criteria of undoped-body symmetric double gate transistors which uses two definitions, one is potential based and the another is charge based definition. In this paper, a novel concept of "crossover point" is introduced, which proves that the charge-based definition is more accurate than the potential based definition. The change in threshold voltage with body thickness variation for a fixed channel length is anomalous as predicted by, potential based definition while it is monotonous for change based definition. The threshold voltage is then extracted from drain currant versus gate voltage characteristics using linear extrapolation and "Third Derivative of Drain-Source Current" method or simply "TD" method. The trend of threshold voltage variation is found some in both the cases which support charge-based definition.

On-Chip Clock Network Skew Measurement using Sub-Sampling

We present a technique for an all-digital on-chip delay measurement system to measure the skews in a clock distribution network. It uses the principle of sub-sampling. Measurements from a prototype fabricated in a 65 nm industrial process, indicate the ability to measure delays with a resolution of 0.5ps and a DNL of 1.2 ps.

A Note on the Genericity of Simultaneous Stabilizability and Pole Assignability

n this paper we study the genericity of simultaneous stabilizability, simultaneous strong stabilizability, and simultaneous pole assignability, in linear multivariable systems. The main results of the paper had been previously established by Ghosh and Byrnes using state-space methods. In contrast, the proofs in the present paper are based on input-output arguments, and are much simpler to follow, especially in the case of simultaneous and simultaneous strong stabilizability. Moreover, the input-output methods used here suggest computationally reliable algorithms for solving these two types of problems. In addition to the main results, we also prove some lemmas on generic greatest common divisors which are of independent interest.

Analysis of avalanche breakdown in bipolar transistors based on majority carrier transportation

This paper describes a new analysis of the avalanche breakdown phenomenon in bipolar transistors for different bias conditions of the emitter-base junction. This analysis revolves around the transportation and storage of majority carriers in the base region. Using this analysis one can compute all the voltage-current characteristics of a transistor under avalanche breakdown.

Analogue-to-quaternary converterst

This paper proposes two circuits for the realization of analogue-to-quaternary converters (AQCs) viz., pipeline AQC and circulation AQC. The proposed AQCs make use of three quaternary circuits namely four level comparator, multiplexer and D flip-flops. These circuits and also the relevant control circuits required in the realization of AQCs are described. A comparison of the two methods is made.

A ternary Schmitt trigger

A new ternary circuit, namely, a ternary Schmitt trigger, is presented. This novel circuit which is based on the well-known lambda diode, is suitable for integration using CMOS technology. The circuit has been simulated using the SPICE 2G Program. The results of the simulation are presented. The circuit offers a high degree of design flexibility. This circuit is expected to be a very useful functional block in the processing of ternary and pseudoternary signals.

Serial quaternary-to-analogue converters

Circuits for realizing serial quaternary-to-analogue converters (QACs) are proposed in this paper. Three techniques are presented based on Shannon-Rack decoder, sample/hold serial digital-to-analogue converter and cyclic digital-to-analogue converter. Circuits for the generation of control signals and the multiplexer required in the realization of the QACs are also described. A comparison of the three methods is made.

A simple firing delay control circuit for bridge converters

A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

Microprocessor Based Sinusoidal PWM Inverter by DMA Transfer

The implementation of three-phase sinusoidal pulse-width-modulated inverter control strategy using microprocessor is discussed in this paper. To save CPU time, the DMA technique is used for transferring the switching pattern from memory to the pulse amplifier and isolation circuits of individual thyristors in the inverter bridge. The method of controlling both voltage and frequency is discussed here.

Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area.