Large-Signal Model for Independent DG MOSFET

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends.

Microscopic Mechanism of 1/f Noise in Graphene: Role of Energy Band Dispersion

A distinctive feature of single-layer graphene is the linearly dispersive energy bands, which in the case of multilayer graphene become parabolic. A simple electrical transport-based probe to differentiate between these two band structures will be immensely valuable, particularly when quantum Hall measurements are difficult, such as in chemically synthesized graphene nanoribbons. Here we show that the flicker noise, or the 1/f noise, in electrical resistance is a sensitive and robust probe to the band structure of graphene. At low temperatures, the dependence of noise magnitude on the carrier density was found to be opposite for the linear and parabolic bands. We explain our data with a comprehensive theoretical model that clarifies several puzzling issues concerning the microscopic origin of flicker noise in graphene field-effect transistors (GraFET).

Si, Si-Ge and the new heterostructure world

Semiconductor heterostructures based on AlAs/GaAs and other III-V compounds have been the focus of active research for some time now. Ih the last decade, a new heterostructure material, the strained Si/SiGe system, has emerged. This heterojunction technology can potentially be integrated into the current VLSI environment with large-scale impact in the growing microelectronics market. Si/SiGe heterojunction bipolar transistors with cut-off frequencies exceeding 100 GHz and other electronic and optical devices with superior properties compared to all-Si technology have been demonstrated in laboratories worldwide.

Electrical and Optical Properties of Diketopyrrolopyrrole-Based Copolymer Interfaces in Thin Film Devices

Two donor acceptor diketopyrrolopyrrole (DPP)-based copolymers (PDPP-BBT and TDPP-BBT) have been synthesized for their application in organic devices such as metal-insulator semiconductor (MIS) diodes and field-effect transistors (FETs). The semiconductor-dielectric interface was characterized by capacitance-voltage and conductance-voltage methods. These measurements yield an interface trap density of 4.2 x 10(12) eV(-1) cm(-2) in TDPP-BBT and 3.5 x 10(12) eV(-1) cm(-2) in PDPP-BBT at the flat-band voltage. The FETs based on these spincoated DPP copolymers display p-channel behavior with hole mobilities of the order 10(-3) cm(2)/(V s). Light scattering studies from PDPP-BBT FETs show almost no change in the Raman spectrum after the devices are allowed to operate at a gate voltage, indicating that the FETs suffer minimal damage due to the metal-polymer contact or the application of an electric field. As a comparison Raman intensity profile from the channel-Au contact layer in pentacene FETs are presented, which show a distinct change before and after biasing.

Synthesis and Self-Assembly of Donor-Acceptor-Donor Based Oligothiophenes and Their Optoelectronic Properties

In this work, the synthesis of an oligothiophene having a donor acceptor donor (D-A-D) chromophore with hydrogen bonding groups is described. The D-A-D molecule was demonstrated to self-organize via intermolecular H-bonding between barbituric acid units. Interactions between the oligothiophene subunits were also found to be important, affording nanoribbons that could be observed by atomic force and transmission electron microscopy. The applicability of the oligothiophene for organic electronic applications was investigated by fabricating organic field-effect transistors (OFETs) and organic photovoltaic devices. The OFET measurements yielded p-type mobility of 7 x 10(-7) cm(2)/(Vs), and when blended with C(60)-PCBM, the photovoltaic efficiency was observed to be 0.18%.

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation

Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint. We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.

Modeling of the Effects of Process Variations on Circuit Delay at 65nm

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.

An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology

Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

Amorphous Hydrogenated Silicon: A Perspective on Circuit Synthesis

Abstract | Non-crystalline or glassy semiconductors are of great research interest for the fabrication of large area electronic systems such as displays and image sensors. Good uniformity over large areas, low temperature fabrication and the promise of low cost electronics on large area mechanically flexible and rigid substrates are some attractive features of these technologies. The article focusses on amorphous hydrogenated silicon thin film transistors, and reviews the problems, solutions and applications of these devices.

Polymer based photo detectors

Recent developments in our laboratory related to polymer-based light sensors are reviewed. The inherent processibility of the active polymer medium is utilized in the implementation of different designs for the opto-electronic applications. The utility of these devices as sensitive photodetectors, image sensors and position sensitive detectors is demonstrated. The schottky-type layer formation at interfaces of polymers such as polyalkylthiophenes and aluminum accompanied by the enhanced photo-induced charge separation due to high local electric field is tapped for some of these device structures. The sensitivity of polymer-based field effect transistors to light also provides a convenient lateral geometry for efficient optical-coupling and control of the transistor state. ne range of these polymer-detectors available with the option of operating in the diode and transistor modes should be an attractive feature for many potential applications.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Growth of branched carbon nanotubes with doped/un-doped intratubular junctions by one-step co-pyrolysis

Branched CNTs with nitrogen doped/un-doped intratubular junctions have been synthesized by a simple one-step co-pyrolysis of hexamethylenetetramine and benzene. The difference in the vapor pressure and the insolubility of the precursors are the keys for the formation of the branched intratubular junctions. The junctions behave like Schottky diodes with nitrogen-doped portion as metal and un-doped portion as p-type semiconductor. The junctions also behave like p-type field effect transistors with a very large on/off ratio.

Investigation of phase separation in bulk heterojunction solar cells via supramolecular chemistry

In this work, we have prepared two donor-acceptor-donor (D-A-D) pi-conjugated oligomers to investigate the effect of phase separation on the performance of bulk heterojunction (BHJ) solar cells. These charge transfer low band gap pi-conjugated oligomers (TTB and NMeTTB) were synthesized by Knoevenagel condensation of terthiophenecarbaldehyde and barbiturate appended pyran derivative. The thin film morphology of both the oligomers and along with electron acceptor 6,6]-phenyl-C60-butyric acid methyl ester (PC61BM) was investigated by atomic force microscopy (AFM) and transmission electron microscopy (TEM). The blend of NMeTTB and PC61BM thin film yield highly ordered thin film, whereas there was clear phase separation between TTB and PC61BM in thin film. The BHJ solar cell was fabricated using a blend of NMeTTB and TTB with PC61BM acceptor in 1:1 ratio as active layer, and a power conversion efficiency of 1.8% was obtained. This device characteristic was compared with device having TTB:PC61BM as active layer, and large difference is observed in photocurrents. This poor performance of TTB in BHJ devices was attributed to the difference in the nanoscale morphology of the corresponding derivatives. We rationalize our findings based on the low charge carrier mobility in organic field-effect transistors and miscibility/phase separation parameter of binary components (oligomers and PC61BM) in the active layer of bulk heterojunction solar cells.

Preliminary study of the effects of carbon nanotubes on Cpu cooling

Managing heat produced by computer processors is an important issue today, especially when the size of processors is decreasing rapidly while the number of transistors in the processor is increasing rapidly. This poster describes a preliminary study of the process of adding carbon nanotubes (CNTs) to a standard silicon paste covering a CPU. Measurements were made in two rounds of tests to compare the rate of cool-down with and without CNTs present. The silicon paste acts as an interface between the CPU and the heat sink, increasing the heat transfer rate away from the CPU. To the silicon paste was added 0.05% by weight of CNTs. These were not aligned. A series of K-type thermocouples was used to measure the temperature as a function of time in the vicinity of the CPU, following its shut-off. An Omega data acquisition system was attached to the thermocouples. The CPU temperature was not measured directly because attachment of a thermocouple would have prevented its automatic shut-off A thermocouple in the paste containing the CNTs actually reached a higher temperature than the standard paste, an effect easily explained. But the rate of cooling with the CNTs was about 4.55% better.