A low-noise low-power noise-adaptive neural amplifier in 0.13um CMOS technology

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.

Multilevel octadecagonal space vector generation for induction motor drives by cascading asymmetric three level inverters

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18 sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three level inverters. By proper selection of DC link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector based PWM techniques are the complete elimination of fifth, seventh, eleventh and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Matlab simulation results and experimental results have been presented in this paper to validate the proposed concept.

Modified current space vector based powerline communication method for distributed inverters interfaced smart grids

The following paper presents a Powerline Communication (PLC) Method for grid interfaced inverters, for smart grid application. The PLC method is based on the concept of the composite vector which involves multiple components rotating at different harmonic frequencies. The pulsed information is modulated on the fundamental component of the grid current as a specific repeating sequence of a particular harmonic. The principle of communication is same as that of power flow, thus reducing the complexity. The power flow and information exchange are simultaneously accomplished by the interfacing inverters based on current programmed vector control, thus eliminating the need for dedicated hardware. Simulation results have been shown for inter-inverter communication, both under ideal and distorted conditions, using various harmonic modulating signals.

CMOS-Compatible and Scalable Deposition of Nanocrystalline Zinc Ferrite Thin Film to Improve Inductance Density of Integrated RF Inductor

Development towards the combination of miniaturization and improved functionality of RFIC has been stalled due to the lack of high-performance integrated inductors. To meet this challenge, integration of magnetic material with high permeability as well as low conductivity is a must. Ferrite films are excellent candidates for RF devices due to their low cost, high resistivity, and low eddy current losses. Unlike its bulk counterpart, nanocrystalline zinc ferrite, because of partial inversion in the spinel structure, exhibits novel magnetic properties suitable for RF applications. However, most scalable ferrite film deposition processes require either high temperature or expensive equipment or both. We report a novel low temperature (< 200 degrees C) solution-based deposition process for obtaining high quality, polycrystalline zinc ferrite thin films (ZFTF) on Si (100) and on CMOS-foundry-fabricated spiral inductor structures, rapidly, using safe solvents and precursors. An enhancement of up to 20% at 5 GHz in the inductance of a fabricated device was achieved due to the deposited ZFTF. Substantial inductance enhancement requires sufficiently thick films and our reported process is capable of depositing smooth, uniform films as thick as similar to 20 mu m just by altering the solution composition. The method is capable of depositing film conformally on a surface with complex geometry. As it requires neither a vacuum system nor any post-deposition processing, the method reported here has a low thermal budget, making it compatible with modern CMOS process flow.

A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications

A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.

Analysis and design of split-capacitor resistive-inductive passive damping for LCL filters in grid-connected inverters

Grid-connected inverters require a third-order LCL filter to meet standards such as the IEEE Std. 519-1992 while being compact and cost-effective. LCL filter introduces resonance, which needs to be damped through active or passive methods. Passive damping schemes have less control complexity and are more reliable. This study explores the split-capacitor resistive-inductive (SC-RL) passive damping scheme. The SC-RL damped LCL filter is modelled using state space approach. Using this model, the power loss and damping are analysed. Based on the analysis, the SC-RL scheme is shown to have lower losses than other simpler passive damping methods. This makes the SC-RL scheme suitable for high power applications. A method for component selection that minimises the power loss in the damping resistors while keeping the system well damped is proposed. The design selection takes into account the influence of switching frequency, resonance frequency and the choice of inductance and capacitance values of the filter on the damping component selection. The use of normalised parameters makes it suitable for a wide range of design applications. Analytical results show the losses and quality factor to be in the range of 0.05-0.1% and 2.0-2.5, respectively, which are validated experimentally.

Harmonic Current Injection based Powerline Communication Method for Grid Connected Single Phase Inverters in Domestic Microgrids

The following paper presents a Powerline Communication (PLC) Method for Single Phase interfaced inverters in domestic microgrids. The PLC method is based on the injection of a repeating sequence of a specific harmonic, which is then modulated on the fundamental component of the grid current supplied by the inverters to the microgrid. The power flow and information exchange are simultaneously accomplished by the grid interacting inverters based on current programmed vector control, hence there is no need for dedicated hardware. Simulation results have been shown for inter-inverter communication under different operating conditions to propose the viability. These simulations have been experimentally validated and the corresponding results have also been presented in the paper.

Analytical Closed-Form Expressions for Harmonic Distortion Corresponding to Novel Switching Sequences for Neutral-Point-Clamped Inverters

Analytical closed-form expressions for harmonic distortion factors corresponding to various pulsewidth modulation (PWM) techniques for a two-level inverter have been reported in the literature. This paper derives such analytical closed-form expressions, pertaining to centered space-vector PWM (CSVPWM) and eight different advanced bus-clamping PWM (ABCPWM) schemes, for a three-level neutral-point-clamped (NPC) inverter. These ABCPWM schemes switch each phase at twice the nominal switching frequency in certain intervals of the line cycle while clamping each phase to one of the dc terminals over certain other intervals. The harmonic spectra of the output voltages, corresponding to the eight ABCPWM schemes, are studied and compared experimentally with that of CSVPWM over the entire modulation range. The measured values of weighted total harmonic distortion (WTHD) of the line voltage V-WTHD are used to validate the analytical closed-form expressions derived. The analytical expressions, pertaining to two of the ABCPWM methods, are also validated by measuring the total harmonic distortion (THD) in the line current I-THD on a 2.2-kW constant volts-per-hertz induction motor drive.

A Grid Simulator to Evaluate Control Performance of Grid-Connected Inverters

Grid simulators are used to test the control performance of grid-connected inverters under a wide range of grid disturbance conditions. In the present work, a three phase back-to-back connected inverter sharing a common dc bus has been programmed as a grid simulator. Three phase balanced disturbance voltages applied to three-phase balanced loads has been considered in the present work. The developed grid simulator can generate three phase balanced voltage sags, voltage swells, frequency deviations and phase jumps. The grid simulator uses a novel disturbance generation algorithm. The algorithm allows the user to reference the disturbance to any of the three phases at any desired phase angle. Further, the exit of the disturbance condition can be referenced to the desired phase angle of any phase by adjusting the duration of the disturbance. The grid simulator hardware has been tested with different loads – a linear purely resistive load, a non-linear diode-bridge load and a grid-connected inverter load.

An Improved Dead-Time Compensation Scheme for Voltage Source Inverters Considering the Device Switching Transition Times

Inverter dead-time, which is meant to prevent shoot-through fault, causes harmonic distortion and change in the fundamental voltage in the inverter output. Typical dead-time compensation schemes ensure that the amplitude of the fundamental output current is as desired, and also improve the current waveform quality significantly. However, even with compensation, the motor line current waveform is observed to be distorted close to the current zero-crossings. The IGBT switching transition times being significantly longer at low currents than at high currents is an important reason for this zero-crossover distortion. Hence, this paper proposes an improved dead-time compensation scheme, which makes use of the measured IGBT switching transition times at low currents. Measured line current waveforms in a 2.2 kW induction motor drive with the proposed compensation scheme are compared against those with the conventional dead-time compensation scheme and without dead-time compensation. The experimental results on the motor drive clearly demonstrate the improvement in the line current waveform quality with the proposed method.

Filter Configuration and PWM Method For Single Phase Inverters with Reduced Conducted EMI Noise

Electromagnetic Interference (EMI) noise is one of the major issues during the design of the grid-tied power converters. Presence of high dv/dt in Common Mode (CM) voltage, excites the parasitic capacitances and causes injection of narrow peaky current to ground. This results in high EMI noise level. A topology consisting of a single phase PWM-rectifier with LCL filter, utilising bipolar PWM method is proposed which reduces the EMI noise level by more than 30dB. This filter topology is shown to be insensitive to the switching delays between the legs of the inverter. The proposed topology eliminates high dv/dt from the dc-bus CM voltage by making it sinusoidal. Hence, the high frequency CM current injection to ground is minimized.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.

Study of Multilevel Sinusoidal PWM methods for Cascaded H-Bridge Multilevel Inverters

This paper is a study of Multilevel Sinusoidal Pulse Width Modulation (MSPWM) methods; Phase Disposition (PD), Alternate Phase Opposition Disposition (APOD), Phase Opposition Disposition (POD) on a single phase Cascaded H-Bridge Multilevel inverter. Various factors such as amplitude modulation index (Ma), frequency modulation index (M-f), phase angle between carrier and reference modulating wave (phi) have been considered for simulation. Variation in these factors and their effect on inverter performance is evaluated. Factors such as DC bus utilization, output r.m.s voltage, total harmonic distortion (%THD), dominant harmonic order, switching losses are evaluated based on simulation results.

Filter Configuration and PWM Method For Single-Phase Inverters With Reduced Conducted EMI Noise

Electromagnetic interference (EMI) noise is one of the major issues during design of grid-tied power converters. A novel LCL filter topology for a single-phase pulsewidth modulation (PWM) rectifier that makes use of bipolar PWM method is proposed for a single-phase to three-phase motor drive power converter. The proposed topology eliminates high dv/dt from the dc-bus common-mode (CM) voltage by making it sinusoidal. Hence, the high-frequency CM current injection to the ground and the motor-side CM current are minimized. The proposed filter configuration makes the system insensitive to circuit non-idealities such as mismatch in inductors values, unequal turn-on and turn-off delays, and dead-time mismatch between the inverter legs. Different variants of the filter topology are compared to establish the effectiveness of the proposed circuit. Experimental results based on the EMI measurement on the grid side and the CM current measurement on the motor side are presented for a 5-kW motor drive. It is shown that the proposed filter topology reduces the EMI noise level by about 35 dB.

Thermal test method for high power three-phase grid-connected inverters

Semiconductor device junction temperatures are maintained within datasheet specified limits to avoid failure in power converters. Burn-in tests are used to ensure this. In inverters, thermal time constants can be large and burn-in tests are required to be performed over long durations of time. At higher power levels, besides increased production cost, the testing requires sources and loads that can handle high power. In this study, a novel method to test a high power three-phase grid-connected inverter is proposed. The method eliminates the need for high power sources and loads. Only energy corresponding to the losses is consumed. The test is done by circulating rated current within the three legs of the inverter. All the phase legs being loaded, the method can be used to test the inverter in both cases of a common or independent cooling arrangement for the inverter phase legs. Further, the method can be used with different inverter configurations - three- or four-wire and for different pulse width modulation (PWM) techniques. The method has been experimentally validated on a 24 kVA inverter for a four-wire configuration that uses sine-triangle PWM and a three-wire configuration that uses conventional space vector PWM.