Woody plant seedling distribution under invasive Lantana camara thickets in a dry-forest plot in Mudumalai, southern India

Lantana camara, a shrub of Central and South American origin, has become invasive across dry forests worldwide. The effect of the thicket-forming habit of L. camara as a dispersal and recruitment barrier in a community of native woody seedlings was examined in a 50-ha permanent plot located in the seasonally dry forest of Mudumalai, southern India. Sixty 100-m(2) plots were enumerated for native woody seedlings between 10-100 cm in height. Of these, 30 plots had no L. camara thickets, while the other 30 had dense thickets. The frequency of occurrence and abundance of seedlings were modelled as a function of dispersal mode (mammal, bird or mechanical) and affinities to forest habitats (dry forest, moist forest or ubiquitous) as well as presence or absence of dense L. camara thickets. Furthermore, frequency of occurrence and abundance of individual species were also compared between thickets and no L. camara. At the community level, L. camara density, dispersal mode and forest habitat affinities of species determined both frequency of occurrence and abundance of seedlings, with the abundance of dry-forest mammal-dispersed species and ubiquitous mechanically dispersed species being significantly lower under L. camara thickets. Phyllanthus emblica and Kydia calycina were found to be significantly less abundant under L. camara, whereas most other species were not affected by the presence of thickets. It was inferred that, by affecting the establishment of native tree seedlings, L. camara thickets could eventually alter the community composition of such forests.

Ramachandran plot on the web

A graphics package has been developed to display the main chain torsion angles phi, psi (phi, Psi); (Ramachandran angles) in a protein of known structure. In addition, the package calculates the Ramachandran angles at the central residue in the stretch of three amino acids having specified the flanking residue types. The package displays the Ramachandran angles along with a detailed analysis output. This software is incorporated with all the protein structures available in the Protein Databank.

Defining the ‘modified Griffin plot’ in vortex-induced vibration: revealing the effect of Reynolds number using controlled damping

In the present work, we study the transverse vortex-induced vibrations of an elastically mounted rigid cylinder in a fluid flow. We employ a technique to accurately control the structural damping, enabling the system to take on both negative and positive damping. This permits a systematic study of the effects of system mass and damping on the peak vibration response. Previous experiments over the last 30 years indicate a large scatter in peak-amplitude data ($A^*$) versus the product of mass–damping ($\alpha$), in the so-called ‘Griffin plot’. A principal result in the present work is the discovery that the data collapse very well if one takes into account the effect of Reynolds number ($\mbox{\textit{Re}}$), as an extra parameter in a modified Griffin plot. Peak amplitudes corresponding to zero damping ($A^*_{{\alpha}{=}0}$), for a compilation of experiments over a wide range of $\mbox{\textit{Re}}\,{=}\,500-33000$, are very well represented by the functional form $A^*_{\alpha{=}0} \,{=}\, f(\mbox{\textit{Re}}) \,{=}\, \log(0.41\,\mbox{\textit{Re}}^{0.36}$). For a given $\mbox{\textit{Re}}$, the amplitude $A^*$ appears to be proportional to a function of mass–damping, $A^*\propto g(\alpha)$, which is a similar function over all $\mbox{\textit{Re}}$. A good best-fit for a wide range of mass–damping and Reynolds number is thus given by the following simple expression, where $A^*\,{=}\, g(\alpha)\,f(\mbox{\textit{Re}})$: \[ A^* \,{=}\,(1 - 1.12\,\alpha + 0.30\,\alpha^2)\,\log (0.41\,\mbox{\textit{Re}}^{0.36}). \] In essence, by using a renormalized parameter, which we define as the ‘modified amplitude’, $A^*_M\,{=}\,A^*/A^*_{\alpha{=}0}$, the previously scattered data collapse very well onto a single curve, $g(\alpha)$, on what we refer to as the ‘modified Griffin plot’. There has also been much debate over the last three decades concerning the validity of using the product of mass and damping (such as $\alpha$) in these problems. Our results indicate that the combined mass–damping parameter ($\alpha$) does indeed collapse peak-amplitude data well, at a given $\mbox{\textit{Re}}$, independent of the precise mass and damping values, for mass ratios down to $m^*\,{=}\,1$.

Precoder Designs for MIMO Broadcast Channels with Imperfect CSI

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A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Channel Precoding for STBCs from Generalized Pseudo Orthogonal Designs

Statistical information about the wireless channel can be used at the transmitter side to enhance the performance of MIMO systems. This paper addresses how the concept of channel precoding can be used to enhance the performance of STBCs from Generalized Pseudo Orthogonal Designs which were first introduced by Zhu and Jafarkhani. Such designs include some important classes of STBCs that are directly derivable from Quasi-Orthogonal Designs and Co-ordinate Interleaved Orthogonal Designs.

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

Towards formal verification of analog mixed signal designs using SPICE circuit simulation traces

An extension to a formal verification approach of hybrid systems is proposed to verify analog and mixed signal (AMS) designs. AMS designs can be formally modeled as hybrid systems and therefore lend themselves to the formal analysis and verification techniques applied to hybrid systems. The proposed approach employs simulation traces obtained from an actual design implementation of AMS circuit blocks (for example, in the form of SPICE netlists) to carry out formal analysis and verification. This enables the same platform used for formally validating an abstract model of an AMS design, to be also used for validating its different refinements and design implementation; thereby, providing a simple route to formal verification at different levels of implementation. The feasibility of the proposed approach is demonstrated with a case study based on a tunnel diode oscillator. Since the device characteristic of a tunnel diode is highly non-linear with a negative resistance region, dynamic behavior of circuits in which it is employed as an element is difficult to model, analyze and verify within a general hybrid system formal verification tool. In the case study presented the formal model and the proposed computational techniques have been incorporated into CheckMate, a formal verification tool based on MATLAB and Simulink-Stateflow Framework from MathWorks.

Low-Delay, High-Rate Nonsquare Complex Orthogonal Designs

The maximal rate of a nonsquare complex orthogonal design for transmit antennas is 1/2 + 1/n if is even and 1/2 + 1/n+1 if is odd and the codes have been constructed for all by Liang (2003) and Lu et al. (2005) to achieve this rate. A lower bound on the decoding delay of maximal-rate complex orthogonal designs has been obtained by Adams et al. (2007) and it is observed that Liang's construction achieves the bound on delay for equal to 1 and 3 modulo 4 while Lu et al.'s construction achieves the bound for n = 0, 1, 3 mod 4. For n = 2 mod 4, Adams et al. (2010) have shown that the minimal decoding delay is twice the lower bound, in which case, both Liang's and Lu et al.'s construction achieve the minimum decoding delay. For large value of, it is observed that the rate is close to half and the decoding delay is very large. A class of rate-1/2 codes with low decoding delay for all has been constructed by Tarokh et al. (1999). In this paper, another class of rate-1/2 codes is constructed for all in which case the decoding delay is half the decoding delay of the rate-1/2 codes given by Tarokh et al. This is achieved by giving first a general construction of square real orthogonal designs which includes as special cases the well-known constructions of Adams, Lax, and Phillips and the construction of Geramita and Pullman, and then making use of it to obtain the desired rate-1/2 codes. For the case of nine transmit antennas, the proposed rate-1/2 code is shown to be of minimal delay. The proposed construction results in designs with zero entries which may have high peak-to-average power ratio and it is shown that by appropriate postmultiplication, a design with no zero entry can be obtained with no change in the code parameters.

SPLIT-STEP FORWARD MILSTEIN METHOD FOR STOCHASTIC DIFFERENTIAL EQUATIONS

In this paper, we consider the problem of computing numerical solutions for stochastic differential equations (SDEs) of Ito form. A fully explicit method, the split-step forward Milstein (SSFM) method, is constructed for solving SDEs. It is proved that the SSFM method is convergent with strong order gamma = 1 in the mean-square sense. The analysis of stability shows that the mean-square stability properties of the method proposed in this paper are an improvement on the mean-square stability properties of the Milstein method and three stage Milstein methods.

Derating Based Hardware Optimizations in Soft Error Tolerant Designs

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e. g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

Rainbow colouring of split and threshold Graphs

A rainbow colouring of a connected graph is a colouring of the edges of the graph, such that every pair of vertices is connected by at least one path in which no two edges are coloured the same. Such a colouring using minimum possible number of colours is called an optimal rainbow colouring, and the minimum number of colours required is called the rainbow connection number of the graph. A Chordal Graph is a graph in which every cycle of length more than 3 has a chord. A Split Graph is a chordal graph whose vertices can be partitioned into a clique and an independent set. A threshold graph is a split graph in which the neighbourhoods of the independent set vertices form a linear order under set inclusion. In this article, we show the following: 1. The problem of deciding whether a graph can be rainbow coloured using 3 colours remains NP-complete even when restricted to the class of split graphs. However, any split graph can be rainbow coloured in linear time using at most one more colour than the optimum. 2. For every integer k ≥ 3, the problem of deciding whether a graph can be rainbow coloured using k colours remains NP-complete even when restricted to the class of chordal graphs. 3. For every positive integer k, threshold graphs with rainbow connection number k can be characterised based on their degree sequence alone. Further, we can optimally rainbow colour a threshold graph in linear time.

On t-designs and bounds relating query complexity to error resilience in locally correctable codes

An n-length block code C is said to be r-query locally correctable, if for any codeword x ∈ C, one can probabilistically recover any one of the n coordinates of the codeword x by querying at most r coordinates of a possibly corrupted version of x. It is known that linear codes whose duals contain 2-designs are locally correctable. In this article, we consider linear codes whose duals contain t-designs for larger t. It is shown here that for such codes, for a given number of queries r, under linear decoding, one can, in general, handle a larger number of corrupted bits. We exhibit to our knowledge, for the first time, a finite length code, whose dual contains 4-designs, which can tolerate a fraction of up to 0.567/r corrupted symbols as against a maximum of 0.5/r in prior constructions. We also present an upper bound that shows that 0.567 is the best possible for this code length and query complexity over this symbol alphabet thereby establishing optimality of this code in this respect. A second result in the article is a finite-length bound which relates the number of queries r and the fraction of errors that can be tolerated, for a locally correctable code that employs a randomized algorithm in which each instance of the algorithm involves t-error correction.