Development of moving magnet type linear motor for dual piston compressor for pulse tube cryocooler

This paper describes the design, fabrication and testing of a moving magnet type linear motor of dual piston configuration for a pulse tube cryocooler for ground applications. Eight radially magnetized segmented magnets were used to form one set of a magnet ring. Four magnet rings of such type were constructed, in which one pair of rings has north-pole on its outer diameter and south-pole on inner diameter, while the other pair is it's complementary. The magnets were mounted with opposite poles together on the magnet holder with an axial moving shaft having a piston mounted on both ends of the shaft. The shaft movement was restricted to the axial direction by using C-clamp type flexures, mounted on both sides of the shaft. The force requirement for driving the compressor was calculated based on which the electrical circuit of motor is designed by proper selection of wire gauge and Ampere-turns. The flexure spring force estimation was done through simulation using ANSYS 11.0 and was verified experimentally; while the magnet spring force was determined experimentally. The motor with mounted piston was tested using a variable voltage and variable frequency power supply capable of driving 140 watts of load.

Strategy for Enhancing the Dielectric Constant of Organic Semiconductors Without Sacrificing Charge Carrier Mobility and Solubility

Current organic semiconductors for organic photovoltaics (OPV) have relative dielectric constants (relative permittivities, epsilon(r)) in the range of 2-4. As a consequence, Coulombically bound electron-hole pairs (excitons) are produced upon absorption of light, giving rise to limited power conversion efficiencies. We introduce a strategy to enhance epsilon(r) of well-known donors and acceptors without breaking conjugation, degrading charge carrier mobility or altering the transport gap. The ability of ethylene glycol (EG) repeating units to rapidly reorient their dipoles with the charge redistributions in the environment was proven via density functional theory (DFT) calculations. Fullerene derivatives functionalized with triethylene glycol side chains were studied for the enhancement of epsilon(r) together with poly(p-phenylene vinylene) and diketo-pyrrolopyrrole based polymers functionalized with similar side chains. The polymers showed a doubling of epsilon(r) with respect to their reference polymers in identical backbone. Fullerene derivatives presented enhancements up to 6 compared with phenyl-C-61-butyric acid methyl ester (PCBM) as the reference. Importantly, the applied modifications did not affect the mobility of electrons and holes and provided excellent solubility in common organic solvents.

Seventeen-Level Inverter Formed by Cascading Flying Capacitor and Floating Capacitor H-Bridges

A multilevel inverter for generating 17 voltage levels using a three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors has been proposed. Various aspects of the proposed inverter like capacitor voltage balancing have been presented in the present paper. Experimental results are presented to study the performance of the proposed converter. The stability of the capacitor balancing algorithm has been verified both during transients and steady-state operation. All the capacitors in this circuit can be balanced instantaneously by using one of the pole voltage combinations. Another advantage of this topology is its ability to generate all the voltages from a single dc-link power supply which enables back-to-back operation of converter. Also, the proposed inverter can be operated at all load power factors and modulation indices. Additional advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels. This configuration has very low dv/dt and common-mode voltage variation.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor

A generalized power tracking algorithm that minimizes power consumption of digital circuits by dynamic control of supply voltage and the body bias is proposed. A direct power monitoring scheme is proposed that does not need any replica and hence can sense total power consumed by load circuit across process, voltage, and temperature corners. Design details and performance of power monitor and tracking algorithm are examined by a simulation framework developed using UMC 90-nm CMOS triple well process. The proposed algorithm with direct power monitor achieves a power savings of 42.2% for activity of 0.02 and 22.4% for activity of 0.04. Experimental results from test chip fabricated in AMS 350 nm process shows power savings of 46.3% and 65% for load circuit operating in super threshold and near sub-threshold region, respectively. Measured resolution of power monitor is around 0.25 mV and it has a power overhead of 2.2% of die power. Issues with loop convergence and design tradeoff for power monitor are also discussed in this paper.

Optical-Phonon-Limited High-Field Transport in Layered Materials

An optical-phonon-limited velocity model has been employed to investigate high-field transport in a selection of layered 2-D materials for both, low-power logic switches with scaled supply voltages, and high-power, high-frequency transistors. Drain currents, effective electron velocities, and intrinsic cutoff frequencies as a function of carrier density have been predicted, thus providing a benchmark for the optical-phonon-limited high-field performance limits of these materials. The optical-phonon-limited carrier velocities for a selection of multi-layers of transition metal dichalcogenides and black phosphorus are found to be modest compared to their n-channel silicon counterparts, questioning the utility of biasing these devices in the source-injection dominated regime. h-BN, at the other end of the spectrum, is shown to be a very promising material for high-frequency, high-power devices, subject to the experimental realization of high carrier densities, primarily due to its large optical-phonon energy. Experimentally extracted saturation velocities from few-layer MoS2 devices show reasonable qualitative and quantitative agreement with the predicted values. The temperature dependence of the measured v(sat) is discussed and compared with the theoretically predicted dependence over a range of temperatures.

Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

A Dual Seven-Level Inverter Supply for an Open-End Winding Induction Motor Drive

This paper develops a seven-level inverter structure for open-end winding induction motor drives. The inverter supply is realized by cascading four two-level and two three-level neutral-point-clamped inverters. The inverter control is designed in such a way that the common-mode voltage (CMV) is eliminated. DC-link capacitor voltage balancing is also achieved by using only the switching-state redundancies. The proposed power circuit structure is modular and therefore suitable for fault-tolerant applications. By appropriately isolating some of the inverters, the drive can be operated during fault conditions in a five-level or a three-level inverter mode, with preserved CMV elimination and DC-link capacitor voltage balancing, within a reduced modulation range.

Theoretical Maximum Limits on Power-Handling Capacity of HVDC Cables

In the case of an ac cable, power transmission is limited by the length of the cable due to the capacitive reactive current component. It is well known that high-voltage direct current (HVDC) cables do not have such limitations. However, insulation-related thermal problems pose a limitation on the power capability of HVDC cables. The author presents a viable theoretical development, a logical extension to Whitehead's theory on thermal limitations of the insulation. The computation of the maximum power-carrying capability of HVDC cables subject to limits on the maximum operable temperature of the insulation is presented. The limitation on the power-carrying capability is closely associated with the electrothermal insulation failure. The effect of environmental interaction by way of external thermal resistance, an important aspect, is also considered in the formulations. The Lagrange multiplier method has been used to handle the ensuing optimization problem. The theory is based on an accepted theory of thermal breakdown in insulation and is an important and a coherent extension of great significance.

A 100MHz to 1GHz, 0.35V to 1.5V supply 256 x 64 SRAM mock using symmetrized 9T SRAM cell with controlled read

In this paper, we present Dynamic Voltage and Frequency Managed 256 x 64 SRAM block in 65nm technology, for frequency ranging from 100MHz to 1GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose Static Noise Margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and Hold Noise Margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag-super-cut-off in stand-by mode without affecting its performance in active mode of operation. The Read Bit Line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

On the duality between rate and power optimizations

Sequence design problems are considered in this paper. The problem of sum power minimization in a spread spectrum system can be reduced to the problem of sum capacity maximization, and vice versa. A solution to one of the problems yields a solution to the other. Subsequently, conceptually simple sequence design algorithms known to hold for the white-noise case are extended to the colored noise case. The algorithms yield an upper bound of 2N - L on the number of sequences where N is the processing gain and L the number of non-interfering subsets of users. If some users (at most N - 1) are allowed to signal along a limited number of multiple dimensions, then N orthogonal sequences suffice.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

Neural network approach for fault location in unbalanced distribution networks with limited measurements

This paper presents an Artificial Neural Network (ANN) approach for locating faults in distribution systems. Different from the traditional Fault Section Estimation methods, the proposed approach uses only limited measurements. Faults are located according to the impedances of their path using a Feed Forward Neural Networks (FFNN). Various practical situations in distribution systems, such as protective devices placed only at the substation, limited measurements available, various types of faults viz., three-phase, line (a, b, c) to ground, line to line (a-b, b-c, c-a) and line to line to ground (a-b-g, b-c-g, c-a-g) faults and a wide range of varying short circuit levels at substation, are considered for studies. A typical IEEE 34 bus practical distribution system with unbalanced loads and with three- and single- phase laterals and a 69 node test feeder with different configurations are considered for studies. The results presented show that the proposed approach of fault location gives close to accurate results in terms of the estimated fault location.

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file. We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine. (C) 2010 Elsevier B.V. All rights reserved.

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay

The use of delayed coefficient adaptation in the least mean square (LMS) algorithm has enabled the design of pipelined architectures for real-time transversal adaptive filtering. However, the convergence speed of this delayed LMS (DLMS) algorithm, when compared with that of the standard LMS algorithm, is degraded and worsens with increase in the adaptation delay. Existing pipelined DLMS architectures have large adaptation delay and hence degraded convergence speed. We in this paper, first present a pipelined DLMS architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph representation of the DLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates, limited only by the delay of a full adder and a 2-to-1 multiplexer. In the second part of this paper, we extend the synthesis methodology described in the first part, to synthesize pipelined DLMS architectures whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the DLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. (C) 1999 Elsevier Science B.V. All rights resented.