Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

Role of Melt Convection on the Thermal Performance of Heat Sinks with Phase Change Material

The role of melt convection oil the performance of beat sinks with Phase Change Material (PCM) is presented in this paper. The beat sink consists of aluminum plate fins embedded in PCM and heat flux is supplied from the bottom. The design of such a heat sink requires optimization with respect to its geometrical parameters. The objective of the optimization is to maximize the heat sink operation time for the prescribed heat flux and the critical chip temperature. The parameters considered for optimization are fin number and fill thickness. The height and base plate thickness of heat sink are kept constant in the present analysis. An enthalpy based CFD model is developed, which is capable Of Simulating phase change and associated melt convection. The CFD model is Coupled with Genetic Algorithm (GA) for carrying out the optimization. Two cases are considered, one without melt convection (conduction regime) and the other with convection. It is found that the geometrical optimizations of heat sinks are different for the two cases, indicating the importance of inch convection in the design of heat sinks with PCMs.

Design of a Multibus-compatible colour graphics subsystem

Colour graphics subsystems can be used in a variety of applications such as high-end business graphics, low-end scientific computations, and for realtime display of process control diagrams. The design of such a subsystem is shown. This subsystem can be added to any Multibus-compatible microcomputer system. The use of an NEC 7220 graphics display controller chip has simplified the design to a considerable extent. CGRAM (CORE graphics on Multibus), a comprehensive subset of the CORE graphics standard package, is supported on the subsystem.

The machinability of a cast aluminium alloy-graphite particle composite

The microstructure of a cast Al---Si alloy-graphite particle composite is examined using optical and analytical scanning electron microscopy. Specimens containing different percentages of graphite were machined by orthogonal planning with 25° and 45° rake angle tools at both 6.5 and 13.2 m min−1. The machining forces are reported and the chip-rake-face friction coefficients and shear flow stresses are calculated. It is shown that the reduction in machining forces with increasing graphite content is due mostly to a decrease in the shear flow stress rather than to lower chip-rake-face friction. Both the polished and the machined surfaces of the composite are rougher than those of the simple alloy, apparently owing to the greater porosity, the tearing out of graphite particles, or the opening of cracks at the graphite particles in the wake of the tool.

Improved damping capacity and machinability of graphite particle-aluminum alloy composites

The damping capacity of cast graphitic aluminum alloy composites has been measured using a torsion pendulum at a constant strain amplitude. It was found that flake-graphite particles dispersed in the matrix of aluminum alloys increased the damping capacity; the improvement was greater, the higher the amount of graphite dispersed in the matrix. At sufficiently high graphite contents the damping capacity of graphitic aluminum composites approaches that of cast iron. The ratio between the damping capacity and the density of graphitic aluminum alloys is higher than cast iron, making them very attractive as light-weight, high-damping materials for possible aircraft applications. Machinability tests on graphite particle-aluminum composites, conducted at speeds of 315 sfm and 525 sfm, showed that the chip length decreased with the amount of graphite of a given size. When the size of graphite was decreased, at a given machining speed, the chip length decreased. Metallographic examination shows that graphite particles act as chip breakers, and are frequently sheared parallel to the plane of the

Analysis of human chorionic gonadotropin-monoclonal antibody interaction in BIAcore

Kinetic studies of macromolecular ligand-ligate interaction have generated ample interest since the advent of plasmon resonance based instruments like BIAcore. Most of the studies reported in literature assume a simple 1 : 1 Langmuir binding and complete reversibility of the system. However we observed that in a high affinity antigen-antibody system [human chorionic gonadotropin-monoclonal antibody (hCG-mAb)] dissociation is insignificant and the sensogram data cannot be used to measure the equilibrium and kinetic parameters. At low concentrations of mAb the complete sensogram could be fitted to a single exponential. Interestingly we found that at higher mAb concentrations, the binding data did not conform to a simple bimolecular model. Instead, the data fitted a two-step model, which may be because of surface heterogeneity of affinity sites. In this paper, we report on the global fit of the sensograms. We have developed a method by which a single two-minute sensogram can be used in high affinity systems to measure the association rate constant of the reaction and the functional capacity of the ligand (hCG) immobilized on the chip. We provide a rational explanation for the discrepancies generally observed in most of the BIAcore sensograms

Redefine: Runtime Reconfigurable Polymorphic ASIC

Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

Sequence Specific Interaction between Promoter DNA and Escherichia coli RNA Polymerase: Comparative Thermodynamic Analysis with One Immobilized Partner

Sequence specific interaction between DNA and protein molecules has been a subject of active investigation for decades now. Here, we have chosen single promoter containing bacteriophage Delta D-III T7 DNA and Escherichia coli RNA polymerase and followed their recognition at the air-water interface by using the surface plasmon resonance (SPR) technique, where the movement of one of the reacting species is restricted by way of arraying them on an immobilized support. For the Langmuir monolayer studies, we used a RNA polymerase with a histidine tag attached to one of its subunits, thus making it an xcellent substrate for Ni(II) ions, while the SPR Studies were done using biotin-labeled DNA immobilized on a streptavidin-coated chip. Detailed analysis of the thermodynamic parameters as a function of concentration and temperature revealed that the interaction of RNA polymerase with T7 DNA is largely entropy driven (83 (+/- 12) kcal mol(-1)) with a positive enthalpy of 13.6 (+/- 3.6) kcal mol(-1), The free energy of reaction determined by SPR and Langmuir-Blodgett technique was -11 (+/- 2) and -15.6 kcal mol(-1), respectively. The ability of these methods to retain the specificity of the recognition process was also established.

A kinetic analysis of the tumor-associated galactopyranosyl-(1→3)-2-acetamido-2-deoxy-α-d-galactopyranoside antigen—lectin interaction

A kinetic study of the tumor-associated galactopyranosyl-(1→3)-2-acetamido-2-deoxy-α-d-galactopyranoside (T-antigen) with lectin peanut agglutinin is described. The disaccharide antigen was synthesized by chemical methods and was functionalized suitably for immobilization onto a carboxy-methylated sensor chip. The ligand immobilized surface was allowed interaction with the lectin peanut agglutinin, which acted as the analyte and the interaction was studied by the surface plasmon resonance method. The ligand—lectin interaction was characterized by the kinetic on-off rates and a bivalent analyte binding model was found to describe the observed kinetic constants. It was identified that the antigen-lectin interaction had a faster association rate constant (k a1) and a slower dissociation rate constant (k d1) in the initial binding step. The subsequent binding step showed much reduced kinetic rates. The antigen-lectin interaction was compared with the kinetic rates of the interaction of a galactopyranosyl-(1→4)-β-d-galactopyranoside derivative and a mannopyranoside derivative with the lectin.

A Petri net model for evaluating packet buffering strategies in a network processor

Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri net model of IP forwarding application on IXP2400 that models the different levels of the memory hierarchy. The cell based interface used to receive and transmit packets in a network processor leads to some small size DRAM accesses. Such narrow accesses to the DRAM expose the bank access latency, reducing the bandwidth that can be realized. With real traces up to 30% of the accesses are smaller than the cell size, resulting in 7.7% reduction in DRAM bandwidth. To overcome this problem, we propose buffering these small chunks of data in the on chip scratchpad memory. This scheme also exploits greater degree of parallelism between different levels of the memory hierarchy. Using real traces from the internet, we show that the transmit rate can be improved by an average of 21% over the base scheme without the use of additional hardware. Further, the impact of different traffic patterns on the network processor resources is studied. Under real traffic conditions, we show that the data bus which connects the off-chip packet buffer to the micro-engines, is the obstacle in achieving higher throughput.

Novel fluorescence detection technique for non-contact temperature sensing in microchip PCR

DNA amplification using Polymerase Chain Reaction (PCR) in a small volume is used in Lab-on-a-chip systems involving DNA manipulation. For few microliters of volume of liquid, it becomes difficult to measure and monitor the thermal profile accurately and reproducibly, which is an essential requirement for successful amplification. Conventional temperature sensors are either not biocompatible or too large and hence positioned away from the liquid leading to calibration errors. In this work we present a fluorescence based detection technique that is completely biocompatible and measures directly the liquid temperature. PCR is demonstrated in a 3 ILL silicon-glass microfabricated device using non-contact induction heating whose temperature is controlled using fluorescence feedback from SYBR green I dye molecules intercalated within sensor DNA. The performance is compared with temperature feedback using a thermocouple sensor. Melting curve followed by gel electrophoresis is used to confirm product specificity after the PCR cycles. (c) 2007 Elsevier B.V. All rights reserved.

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router

A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.

Transcription of Human Resistin Gene Involves an Interaction of Sp1 with Peroxisome Proliferator-Activating Receptor Gamma (PPAR gamma)

Background: Resistin is a cysteine rich protein, mainly expressed and secreted by circulating human mononuclear cells. While several factors responsible for transcription of mouse resistin gene have been identified, not much is known about the factors responsible for the differential expression of human resistin.Methodology/Principal Finding: We show that the minimal promoter of human resistin lies within similar to 80 bp sequence upstream of the transcriptional start site (-240) whereas binding sites for cRel, CCAAT enhancer binding protein alpha (C/EBP-alpha), activating transcription factor 2 (ATF-2) and activator protein 1 (AP-1) transcription factors, important for induced expression, are present within sequences up to -619. Specificity Protein 1(Sp1) binding site (-276 to -295) is also present and an interaction of Sp1 with peroxisome proliferator activating receptor gamma (PPAR gamma) is necessary for constitutive expression in U937 cells. Indeed co-immunoprecipitation assay demonstrated a direct physical interaction of Sp1 with PPAR gamma in whole cell extracts of U937 cells. Phorbol myristate acetate (PMA) upregulated the expression of resistin mRNA in U937 cells by increasing the recruitment of Sp1, ATF-2 and PPAR gamma on the resistin gene promoter. Furthermore, PMA stimulation of U937 cells resulted in the disruption of Sp1 and PPAR gamma interaction. Chromatin immunoprecipitation (ChIP) assay confirmed the recruitment of transcription factors phospho ATF-2, Sp1, Sp3, PPAR gamma, chromatin modifier histone deacetylase 1 (HDAC1) and the acetylated form of histone H3 but not cRel, C/EBP-alpha and phospho c-Jun during resistingene transcription.Conclusion: Our findings suggest a complex interplay of Sp1 and PPAR gamma along with other transcription factors that drives the expression of resistin in human monocytic U937 cells.

Sequence design for symbol-asynchronous CDMA with power or rate constraints

Sequence design and resource allocation for a symbol-asynchronous chip-synchronous code division multiple access (CDMA) system is considered in this paper. A simple lower bound on the minimum sum-power required for a non-oversized system, based on the best achievable for a non-spread system, and an analogous upper bound on the sum rate are first summarised. Subsequently, an algorithm of Sundaresan and Padakandla is shown to achieve the lower bound on minimum sum power (upper bound on sum rate, respectively). Analogous to the synchronous case, by splitting oversized users in a system with processing gain N, a system with no oversized users is easily obtained, and the lower bound on sum power (upper bound on sum rate, respectively) is shown to be achieved by using N orthogonal sequences. The total number of splits is at most N - 1.

A cost effective pipelined divider for double precision floating point number

he growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency; pipelined floating point dividers. Solutions available in the literature use large lookup table for double precision floating point operations.In this paper, we propose a cost effective, fixed latency pipelined divider using modified Taylor-series expansion for double precision floating point operations. We reduce chip area by using a smaller lookup table. We show that the latency of the proposed divider is 49.4 times the latency of a full-adder. The proposed divider reduces chip area by about 81% than the pipelined divider in [9] which is based on modified Taylor-series.