A cost effective pipelined divider for double precision floating point number
Contribuinte(s) |
Werner, B |
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Data(s) |
2006
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Resumo |
he growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency; pipelined floating point dividers. Solutions available in the literature use large lookup table for double precision floating point operations.In this paper, we propose a cost effective, fixed latency pipelined divider using modified Taylor-series expansion for double precision floating point operations. We reduce chip area by using a smaller lookup table. We show that the latency of the proposed divider is 49.4 times the latency of a full-adder. The proposed divider reduces chip area by about 81% than the pipelined divider in [9] which is based on modified Taylor-series. |
Formato |
application/pdf |
Identificador |
http://eprints.iisc.ernet.in/30456/1/04019504.pdf Singh, Sandeep B and Biswas, Jayanta and Nandy, SK (2006) A cost effective pipelined divider for double precision floating point number. In: 17th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Steamboat Springs,, Sep 11-13, 2006, Steamboat Springs, CO, pp. 132-137. |
Publicador |
IEEE |
Relação |
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4019504 http://eprints.iisc.ernet.in/30456/ |
Palavras-Chave | #Others |
Tipo |
Conference Paper PeerReviewed |