A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications

A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.

Analysis of OSNR Requirements for Higher Modulation Schemes for Various Local Oscillator Powers

To meet the growing demands of data traffic in long haul communication, it is necessary to efficiently use the low-loss region(C-band) of the optical spectrum, by increasing the no. of optical channels and increasing the bit rate on each channel But narrow pulses occupy higher spectral bandwidth. To circumvent this problem, higher order modulation schemes such as QPSK and QAM can be used to modulate the bits, which increases the spectral efficiency without demanding any extra spectral bandwidth. On the receiver side, to meet a satisfy, a given BER, the received optical signal requires to have minimum OSNR. In our study in this paper, we analyses for different modulation schemes, the OSNR required with and without preamplifier. The theoretical limit of OSNR requirement for a modulation scheme is compared for a given link length by varying the local oscillator (LO) power. Our analysis shows that as we increase the local oscillator (LO) power, the OSNR requirement decreases for a given BER. Also a combination of preamplifier and local oscillator (LO) gives the OSNR closest to theoretical limit.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

A do-it-yourself (DIY) switched mode power conversion laboratory

In the education of physical sciences, the role of the laboratory cannot be overemphasised. It is the laboratory exercises which enable the student to assimilate the theoretical basis, verify the same through bench-top experiments, and internalize the subject discipline to acquire mastery of the same. However the resources essential to put together such an environment is substantial. As a result, the students go through a curriculum which is wanting in this respect. This paper presents a low cost alternative to impart such an experience to the student aimed at the subject of switched mode power conversion. The resources are based on an open source circuit simulator (Sequel) developed at IIT Mumbai, and inexpensive construction kits developed at IISc Bangalore. The Sequel programme developed by IIT Mumbai, is a circuit simulation program under linux operating system distributed free of charge. The construction kits developed at IISc Bangalore, is fully documented for anyone to assemble these circuit which minimal equipment such as soldering iron, multimeter, power supply etc. This paper puts together a simple forward dc to dc converter as a vehicle to introduce the programming under sequel to evaluate the transient performance and small signal dynamic model of the same. Bench tests on the assembled construction kit may be done by the student for study of operation, transient performance and closed loop stability margins etc.

Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Fast Multiple Access Selection through variable power transmissions

Many wireless applications demand a fast mechanism to detect the packet from a node with the highest priority ("best node") only, while packets from nodes with lower priority are irrelevant. In this paper, we introduce an extremely fast contention-based multiple access algorithm that selects the best node and requires only local information of the priorities of the nodes. The algorithm, which we call Variable Power Multiple Access Selection (VP-MAS), uses the local channel state information from the accessing nodes to the receiver, and maps the priorities onto the receive power. It is based on a key result that shows that mapping onto a set of discrete receive power levels is optimal, when the power levels are chosen to exploit packet capture that inherently occurs in a wireless physical layer. The VP-MAS algorithm adjusts the expected number of users that contend in each step and their respective transmission powers, depending on whether previous transmission attempts resulted in capture, idle channel, or collision. We also show how reliable information regarding the total received power at the receiver can be used to improve the algorithm by enhancing the feedback mechanism. The algorithm detects the packet from the best node in 1.5 to 2.1 slots, which is considerably lower than the 2.43 slot average achieved by the best algorithm known to date.

On the nature of power flow equations in security analysis

The power system network is assumed to be in steady-state even during low frequency transients. However, depending on generator dynamics, and toad and control characteristics, the system model and the nature of power flow equations can vary The nature of power flow equations describing the system during a contingency is investigated in detail. It is shown that under some mild assumptions on load-voltage characteristics, the power flow equations can be decoupled in an exact manner. When the generator dynamics are considered, the solutions for the load voltages are exact if load nodes are not directly connected to each other

Some aspects of multilevel load-frequency control of a power system

The application of multilevel control strategies for load-frequency control of interconnected power systems is assuming importance. A large multiarea power system may be viewed as an interconnection of several lower-order subsystems, with possible change of interconnection pattern during operation. The solution of the control problem involves the design of a set of local optimal controllers for the individual areas, in a completely decentralised environment, plus a global controller to provide the corrective signal to account for interconnection effects. A global controller, based on the least-square-error principle suggested by Siljak and Sundareshan, has been applied for the LFC problem. A more recent work utilises certain possible beneficial aspects of interconnection to permit more desirable system performances. The paper reports the application of the latter strategy to LFC of a two-area power system. The power-system model studied includes the effects of excitation system and governor controls. A comparison of the two strategies is also made.

Optimum Evaluation of Reactive Power Requirements in Power Distribution-Systems

This paper presents three methodologies for determining optimum locations and magnitudes of reactive power compensation in power distribution systems. Method I and Method II are suitable for complex distribution systems with a combination of both radial and ring-main feeders and having different voltage levels. Method III is suitable for low-tension single voltage level radial feeders. Method I is based on an iterative scheme with successive powerflow analyses, with formulation and solution of the optimization problem using linear programming. Method II and Method III are essentially based on the steady state performance of distribution systems. These methods are simple to implement and yield satisfactory results comparable with the results of Method I. The proposed methods have been applied to a few distribution systems, and results obtained for two typical systems are presented for illustration purposes.

Optimal scheduling of hydro-thermal power systems under shortage

The problem of optimal scheduling of the generation of a hydro-thermal power system that is faced with a shortage of energy is studied. The deterministic version of the problem is first analyzed, and the results are then extended to cases where the loads and the hydro inflows are random variables.

Transient state work fluctuation theorem for a classical harmonic oscillator linearly coupled to a harmonic bath

Based on a Hamiltonian description we present a rigorous derivation of the transient state work fluctuation theorem and the Jarzynski equality for a classical harmonic oscillator linearly coupled to a harmonic heat bath, which is dragged by an external agent. Coupling with the bath makes the dynamics dissipative. Since we do not assume anything about the spectral nature of the harmonic bath the derivation is not restricted only to the Ohmic bath, rather it is more general, for a non-Ohmic bath. We also derive expressions of the average work done and the variance of the work done in terms of the two-time correlation function of the fluctuations of the position of the harmonic oscillator. In the case of an Ohmic bath, we use these relations to evaluate the average work done and the variance of the work done analytically and verify the transient state work fluctuation theorem quantitatively. Actually these relations have far-reaching consequences. They can be used to numerically evaluate the average work done and the variance of the work done in the case of a non-Ohmic bath when analytical evaluation is not possible.

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

A Current Source Inverter Fed Induction Motor Drive with Power Factor Angle Control Using Microprocessor

This paper describes a method of adjusting the stator power factor angle for the control of an induction motor fed from a current source inverter (CSI) based on the concept of space vectors (or park vectors). It is shown that under steady state, if the torque angle is kept constant over the entire operating range, it has the advantage of keeping the slip frequency constant. This can be utilized to dispose of the speed feedback and simplify the control scheme for the drive, such that the stator voltage integral zero crossings alone can be used as a feedback for deciding the triggering instants of the CSI thyristors under stable operation of the system. A closed-loop control strategy is developed for the drive based on this principle, using a microprocessor-based control system and is implemented on a laboratory prototype CSI fed induction motor drive.

An adaptive power-system stabiliser which cancels the negative damping torque of a synchronous generator

The paper presents a new criterion for designing a power-system stabiliser, which is that it should cancel the negative damping torque inherent in a synchronous generator and automatic voltage regulator. The method arises from analysis based on the properties of tensor invariance, but it is easily implemented, and leads to the design of an adaptive controller. Extensive computations and simulation have been performed, and laboratory tests have been conducted on a computer-controlled micromachine system. Results are presented illustrating the effectiveness of the adaptive stabiliser.

Representations and properties of para-Bose oscillator operators. I. Energy position and momentum eigenstates

Para-Bose commutation relations are related to the SL(2,R) Lie algebra. The irreducible representation [script D]alpha of the para-Bose system is obtained as the direct sum Dbeta[direct-sum]Dbeta+1/2 of the representations of the SL(2,R) Lie algebra. The position and momentum eigenstates are then obtained in this representation [script D]alpha, using the matrix mechanical method. The orthogonality, completeness, and the overlap of these eigenstates are derived. The momentum eigenstates are also derived using the wave mechanical method by specifying the domain of the definition of the momentum operator in addition to giving it a formal differential expression. By a careful consideration in this manner we find that the two apparently different solutions obtained by Ohnuki and Kamefuchi in this context are actually unitarily equivalent. Journal of Mathematical Physics is copyrighted by The American Institute of Physics.