Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

Threshold voltage modeling under size quantization for ultra-thin silicon double-gate metal-oxide-semiconductor field-effect transistor

We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.

Analysis of size quantization and temperature effects on the threshold voltage of thin silicon film double-gate metal-oxide-semiconductor field-effect transistor (MOSFET)

In this paper, we analyze the combined effects of size quantization and device temperature variations (T = 50K to 400 K) on the intrinsic carrier concentration (n(i)), electron concentration (n) and thereby on the threshold voltage (V-th) for thin silicon film (t(si) = 1 nm to 10 nm) based fully-depleted Double-Gate Silicon-on-Insulator MOSFETs. The threshold voltage (V-th) is defined as the gate voltage (V-g) at which the potential at the center of the channel (Phi(c)) begins to saturate (Phi(c) = Phi(c(sat))). It is shown that in the strong quantum confinement regime (t(si) <= 3nm), the effects of size quantization far over-ride the effects of temperature variations on the total change in band-gap (Delta E-g(eff)), intrinsic carrier concentration (n(i)), electron concentration (n), Phi(c(sat)) and the threshold voltage (V-th). On the other hand, for t(si) >= 4 nm, it is shown that size quantization effects recede with increasing t(si), while the effects of temperature variations become increasingly significant. Through detailed analysis, a physical model for the threshold voltage is presented both for the undoped and doped cases valid over a wide-range of device temperatures, silicon film thicknesses and substrate doping densities. Both in the undoped and doped cases, it is shown that the threshold voltage strongly depends on the channel charge density and that it is independent of incomplete ionization effects, at lower device temperatures. The results are compared with the published work available in literature, and it is shown that the present approach incorporates quantization and temperature effects over the entire temperature range. We also present an analytical model for V-th as a function of device temperature (T). (C) 2013 AIP Publishing LLC.

Performance Analysis of Strained Monolayer MoS2 MOSFET

We present a computational study on the impact of tensile/compressive uniaxial (epsilon(xx)) and biaxial (epsilon(xx) = epsilon(yy)) strain on monolayer MoS2, n-, and p-MOSFETs. The material properties like band structure, carrier effective mass, and the multiband Hamiltonian of the channel are evaluated using the density functional theory. Using these parameters, self-consistent Poisson-Schrodinger solution under the nonequilibrium Green's function formalism is carried out to simulate the MOS device characteristics. 1.75% uniaxial tensile strain is found to provide a minor (6%) ON current improvement for the n-MOSFET, whereas same amount of biaxial tensile strain is found to considerably improve the p-MOSFET ON currents by 2-3 times. Compressive strain, however, degrades both n-MOS and p-MOS devices performance. It is also observed that the improvement in p-MOSFET can be attained only when the channel material becomes indirect gap in nature. We further study the performance degradation in the quasi-ballistic long-channel regime using a projected current method.

Negative differential resistance and effect of defects and deformations in MoS2 armchair nanoribbon metal-oxide-semiconductor field effect transistor

In this work, we present a study on the negative differential resistance (NDR) behavior and the impact of various deformations (like ripple, twist, wrap) and defects like vacancies and edge roughness on the electronic properties of short-channel MoS2 armchair nanoribbon MOSFETs. The effect of deformation (3 degrees-7 degrees twist or wrap and 0.3-0.7 angstrom ripple amplitude) and defects on a 10 nm MoS2 ANR FET is evaluated by the density functional tight binding theory and the non-equilibrium Green's function approach. We study the channel density of states, transmission spectra, and the I-D-V-D characteristics of such devices under the varying conditions, with focus on the NDR behavior. Our results show significant change in the NDR peak to valley ratio and the NDR window with such minor intrinsic deformations, especially with the ripple. (C) 2013 AIP Publishing LLC.

A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry

Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level of the existing models. In the proposed model, the surface potential relationship is used to include the drain-induced barrier lowering, channel length modulation, velocity saturation, and quantum mechanical effect in the long-channel model and good agreement is observed with the technology computer aided design simulation results.

Phonon scattering limited performance of monolayer MoS2 and WSe2 n-MOSFET

In this paper we show the effect of electron-phonon scattering on the performance of monolayer (1L) MoS2 and WSe2 channel based n-MOSFETs. Electronic properties of the channel materials are evaluated using the local density approximation (LDA) in density functional theory (DFT). For phonon dispersion we employ the small displacement / frozen phonon calculations in DFT. Thereafter using the non-equilibrium Green's function (NEGF) formalism, we study the effect of electron-phonon scattering and the contribution of various phonon modes on the performance of such devices. It is found that the performance of the WSe2 device is less impacted by phonon scattering, showing a ballisticity of 83% for 1L-WSe2 FET for channel length of 10 nm. Though 1L-MoS2 FET of similar dimension shows a lesser ballisticity of 75%. Also in the presence of scattering there exist a a 21-36% increase in the intrinsic delay time (tau) and a 10-18% reduction in peak transconductance (g(m)) for WSe2 and MoS2 devices respectively. (C) 2015 Author(s).

Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.