Replication of Japanese encephalitis virus in mouse brain induces alterations in lymphocyte response

The experimental model using intracerebral (i.c.) challenge was employed in many studies evaluating the protection against disease induced by Japanese encephalitis virus (JEV). We investigated alterations in peripheral lymphocyte response caused by i.c. infection of mice with JEV. Splenocytes from the i.c.-infected mice showed suppressed proliferative response to concanavalin A (con A) and anti-CD3 antibody stimulation. At the same time, the expression of CD25 (IL-2R) and production of IL-2 was inhibited. Addition of anti-CD28 antibody restored the decreased anti-CD3 antibody-mediated proliferation in the splenocytes. Moreover, the number of con A-stimulated cells secreting IL-4 was significantly reduced in splenocytes from i.c.-infected mice. These studies suggested that the i.c. infection with JEV might involve additional immune modulation effects due to massive virus replication in the brain.

RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

Japanese Encephalitis Virus Utilizes the Canonical Pathway To Activate NF-kappa B but It Utilizes the Type I Interferon Pathway To Induce Major Histocompatibility Complex Class I Expression in Mouse Embryonic Fibroblasts

Flaviviruses have been shown to induce cell surface expression of major histocompatibility complex class I (MHC-I) through the activation of NF-kappa B. Using IKK1(-/-), IKK2(-/-), NEMO-/-, and IKK1-/- IKK2-/- double mutant as well as p50(-/-) RelA(-/-) cRel(-/-) triple mutant mouse embryonic fibroblasts infected with Japanese encephalitis virus (JEV), we show that this flavivirus utilizes the canonical pathway to activate NF-kappa B in an IKK2- and NEMO-, but not IKK1-, dependent manner. NF-kappa B DNA binding activity induced upon virus infection was shown to be composed of RelA: p50 dimers in these fibroblasts. Type I interferon (IFN) production was significantly decreased but not completely abolished upon virus infection in cells defective in NF-kappa B activation. In contrast, induction of classical MHC-I (class 1a) genes and their cell surface expression remained unaffected in these NF-kappa B-defective cells. However, MHC-I induction was impaired in IFNAR(-/-) cells that lack the alpha/beta IFN receptor, indicating a dominant role of type I IFNs but not NF-kappa B for the induction of MHC-I molecules by Japanese encephalitis virus. Our further analysis revealed that the residual type I IFN signaling in NF-kappa B-deficient cells is sufficient to drive MHC-I gene expression upon virus infection in mouse embryonic fibroblasts. However, NF-kappa B could indirectly regulate MHC-I expression, since JEV-induced type I IFN expression was found to be critically dependent on it.

High performance VLSI architecture design for H.264 CAVLC decoder

H.264 video standard achieves high quality video along with high data compression when compared to other existing video standards. H.264 uses context-based adaptive variable length coding (CAVLC) to code residual data in Baseline profile. In this paper we describe a novel architecture for CAVLC decoder including coeff-token decoder, level decoder total-zeros decoder and run-before decoder UMC library in 0.13 mu CMOS technology is used to synthesize the proposed design. The proposed design reduces chip area and improves critical path performance of CAVLC decoder in comparison with [1]. Macroblock level (including luma and chroma) pipeline processing for CAVLC is implemented with an average of 141 cycles (including pipeline buffering) per macroblock at 250MHz clock frequency. To compare our results with [1] clock frequency is constrained to 125MHz. The area required for the proposed architecture is 17586 gates, which is 22.1% improvement in comparison to [1]. We obtain a throughput of 1.73 * 10(6) macroblocks/second, which is 28% higher than that reported in [1]. The proposed design meets the processing requirement of 1080HD [5] video at 30frames/seconds.

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

Architecture of Run-time Reconfigurable Channel Decoder

Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

Design and performance evaluation of a systolic architecture for hidden-surface removal

In this paper, we propose a systolic architecture for hidden-surface removal. Systolic architecture is a kind of parallel architecture best known for its easy VLSI implementability. After discussing the design details of the architecture, we present the results of the simulation experiments conducted in order to evaluate the performance of the architecture.

Parallel min-cut placement on reduced hardware SIMD architecture.

Massively parallel SIMD computing is applied to obtain an order of magnitude improvement in the executional speed of an important algorithm in VLSI design automation. The physical design of a VLSI circuit involves logic module placement as a subtask. The paper is concerned with accelerating the well known Min-cut placement technique for logic cell placement. The inherent parallelism of the Min-cut algorithm is identified, and it is shown that a parallel machine based on the efficient execution of the placement procedure.

A fault-tolerant multi-transputer architecture

A new fault-tolerant multi-transputer architecture capable of tolerating failure of any one component in the system is described. In the proposed architecture the processing nodes are automatically reconfigured in the event of a fault and the computations continue from the stage where the fault occurred. The process of reconfiguration is transparent to the user, and the identity of the failed component is communicated to the user along with the results of computations. Parallel solution of a typical engineering problem involving solution of Laplace's equation by the boundary element method has been implemented. The performance of the architecture in the event of faults has been investigated.

Architecture of Physalis Mottle Tymovirus as Probed by Monoclonal Antibodies and Cross-Linking Studies

Physalis mottle tymovirus (previously named belladonna mottle virus, Iowa strain) RNA was cross-linked to its coat protein by exposure of the intact virus to ultraviolet light. The site of cross-linking of the coat protein with the RNA was identified as Lys-10 by sequencing the oligonucleotide-linked tryptic peptide obtained upon HPLC separation subsequent to enzymetic digestion of the cross-linked and dissociated virus. Three monoclonal antibodies PA3B2, PB5G9, and PF12C9, obtained using denatured coat protein as antigen, cross-reacted effectively with the intact virus indicating that the epitopes recognized by these monoclonals are on the surface of the virus. Using the peptides generated by digestion with CNBr, clostripain, V-8 protease, or trypsin and a recombinant protein lacking the N-terminal 21 residues expressed from a cDNA clone, it was shown that PA3B2 recognizes the sequence 22-36 on the coat protein while PB5G9 and PF12C9 recognize region 75-110. These results suggest that Lys-10 is one of the specific sites through which the RNA interacts in the intact virus. The polypeptide segment (region 22-36) following this buried portion as well as the epitope within the region 75-110 are exposed in the intact virus. These observations are consistent with the canonical β-barrel structure observed in certain other plant viruses.

Area Optimized H.264 Intra Prediction Architecture for 1080p HD Resolution

High performance video standards use prediction techniques to achieve high picture quality at low bit rates. The type of prediction decides the bit rates and the image quality. Intra Prediction achieves high video quality with significant reduction in bit rate. This paper present an area optimized architecture for Intra prediction, for H.264 decoding at HDTV resolution with a target of achieving 60 fps. The architecture was validated on Virtex-5 FPGA based platform. The architecture achieves a frame rate of 64 fps. The architecture is based on multi-level memory hierarchy to reduce latency and ensure optimum resources utilization. It removes redundancy by reusing same functional blocks across different modes. The proposed architecture uses only 13% of the total LUTs available on the Xilinx FPGA XC5VLX50T.

Cytotoxic T lymphocytes raised against Japanese encephalitis virus: effector cell phenotype, target specificity and in vitro virus clearance.

Several H-2 defined cell lines were examined for their ability to support infection and replication of Japanese encephalitis virus (JEV) before their use in in vitro and in vivo stimulation protocols for generating cytotoxic T lymphocytes (CTLs) against JEV. Among II different cell lines tested, two H-2(d) macrophage tumour lines (P388D1, RAW 264.7), an H-2(d) hybridoma (Sp2/0), an H-2K(k)D(d) neuroblastoma (Neuro 2a), and H-2(k) fibroblast cell line (L929) were found to support JEV infection and replication. These cell lines were used to generate anti-JEV CTLs by using in vivo immunization followed by in vitro stimulation of BALB/c mice. We observed that not only syngeneic and allogeneic infected cells but also JEV-infected xenogeneic cells could prime BALB/c mice for the generation of JEV-specific CTLs upon subsequent in vitro stimulation of splenocytes with JEV-infected syngeneic cells. Although infected xenogeneic cells were used for immunization, the anti-JEV effecters that were generated lysed infected syngeneic targets but not JEV-infected xenogeneic or allogeneic target cells in a 5h Cr-51 release assay. These anti-JEV effecters recognized syngeneic target cells infected with West Nile virus to a lesser extent and were shown to be Lyt-2.2(+) T cells. The results of unlabelled cold target competition studies suggested alterations in the cell surface expression of viral antigenic determinants recognized by these CTLs. We further demonstrate that the JEV-specific CTLs generated could virtually block the release of infectious virus particles from infected P388D1 and Neuro 2a cells in vitro.

Diacetylenic lipid tubules:experimental evidence for a chiral molecular architecture

Molecular self-assembly is of key importance for the rational design of advanced materials. To investigate the causal relation between molecular structure and the consequent self-assembled microstructure, self-assembled tubules of diacetylenic lipids were studied. Circular-dichroism studies give experimental evidence that the formation of tubules is driven by chiral molecular packing, in agreement with recent theories of tubules. On the basis of these results, a molecular mechanism for the formation of tubules is proposed.