An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.

Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change

In a wireless receiver, a down-converted RF signal undergoes a transient phase shift, when the gain state is changed to adjust for varying conditions in transmission and propagation. A method is developed, in which such phase shifts are detected asynchronously, and their undesirable effects on the bit error rate are corrected. The method was developed for and used in, the system-level characterization and calibration of a 65-nm CMOS UHF receiver. The phase-shifts associated with specific gain-state transitions were measured within a test framework, and used in the baseband signal processing blocks to compensate for errors, whenever the receiver anticipated a gain-state transition.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Time-Based All-Digital Technique for Analog Built-in Self-Test

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.

Transfer free suspended graphene devices on silicon using electrodeposited copper

Transfer free processes using Cu films greatly simplify the fabrication of reliable suspended graphene devices. In this paper, the authors report on the use of electrodeposited Cu films on Si for transfer free fabrication of suspended graphene devices. The quality of graphene layers on optimized electrodeposited Cu and Cu foil are found to be the same. By selectively etching the underlying Cu, the authors have realized by a transfer free process metal contacted, suspended graphene beams up to 50 mu m in length directly on Si. The suspended graphene beams do not show any increase in defect levels over the as grown state indicating the efficiency of the transfer free process. Measured room temperature electronic mobilities of up to 5200 cm(2)/V.s show that this simpler and CMOS compatible route has the potential to replace the foil based route for such suspended nano and micro electromechanical device arrays. (C) 2014 American Vacuum Society.

Design of a Low Power 64 Point FFT Architecture for WLAN Applications

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit

In this paper we propose a fully parallel 64K point radix-4(4) FFT processor. The radix-4(4) parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. The radix-4(4) block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. The resultant 64K point FFT processor shows significant reduction in intermediate memory but with increased hardware complexity. Compared to the state-of-art implementation 5], our architecture shows reduced latency with comparable throughput and area. The 64K point FFT architecture was synthesized using a 130nm CMOS technology which resulted in a throughput of 1.4 GSPS and latency of 47.7 mu s with a maximum clock frequency of 350MHz. When compared to 5], the latency is reduced by 303 mu s with 50.8% reduction in area.

Influence of O-2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

HfO2 thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O-2 flow rate, during vaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O-2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O-2 flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO2 films deposited at two O-2 flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO2 film deposited at 3 SCCM O-2 flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices.

Quantitative Strain and Compositional Studies of InxGa1-xAs Epilayer in a GaAs-based pHEMT Device Structure by TEM Techniques

In GaAs-based pseudomorphic high-electron mobility transistor device structures, strain and composition of the InxGa1 (-) As-x channel layer are very important as they influence the electronic properties of these devices. In this context, transmission electron microscopy techniques such as (002) dark-field imaging, high-resolution transmission electron microscopy (HRTEM) imaging, scanning transmission electron microscopy-high angle annular dark field (STEM-HAADF) imaging and selected area diffraction, are useful. A quantitative comparative study using these techniques is relevant for assessing the merits and limitations of the respective techniques. In this article, we have investigated strain and composition of the InxGa1 (-) As-x layer with the mentioned techniques and compared the results. The HRTEM images were investigated with strain state analysis. The indium content in this layer was quantified by HAADF imaging and correlated with STEM simulations. The studies showed that the InxGa1 (-) As-x channel layer was pseudomorphically grown leading to tetragonal strain along the 001] growth direction and that the average indium content (x) in the epilayer is similar to 0.12. We found consistency in the results obtained using various methods of analysis.

First principles study of metal contacts to monolayer black phosphorous

Atomically thin layered black phosphorous (BP) has recently appeared as an alternative to the transitional metal dichalcogenides for future channel material in a metal-oxide-semiconductor transistor due to its lower carrier effective mass. Investigation of the electronic property of source/drain contact involving metal and two-dimensional material is essential as it impacts the transistor performance. In this paper, we perform a systematic and rigorous study to evaluate the Ohmic nature of the side-contact formed by the monolayer BP (mBP) and metals (gold, titanium, and palladium), which are commonly used in experiments. Employing the Density Functional Theory, we analyse the potential barrier, charge transfer and atomic orbital overlap at the metal-mBP interface in an optimized structure to understand how efficiently carriers could be injected from metal contact to the mBP channel. Our analysis shows that gold forms a Schottky contact with a higher tunnel barrier at the interface in comparison to the titanium and palladium. mBP contact with palladium is found to be purely Ohmic, where as titanium contact demonstrates an intermediate behaviour. (C) 2014 AIP Publishing LLC.

Herringbone to cofacial solid state packing via H-bonding in diketopyrrolopyrrole (DPP) based molecular crystals: influence on charge transport

Themono-alkylation of DPP derivatives leads to cofacial pi-pi stacking via H-bonding unlike their di-alkylated counterparts, which exhibit a classical herringbone packing pattern. Single crystal organic field-effect transistor (OFET) measurements reveal a significant enhancement of charge carrier mobility for mono-hexyl DPP derivatives.

Differential Multi-phase DLL for Reconfigurable Radio Frequency Synthesizer

A multi phase, delay-locked loop (DLL) based frequency synthesizer is designed for harmonic rejection mixing in reconfigurable radios. This frequency synthesizer uses a 1 GHz input reference frequency, and achieves <= 20ns settling time by utilizing a wide loop bandwidth. The circuit has been designed in 0.13-mu m CMOS technology. It is designed for a frequency range of 500 MHz to 3 GHz with stuck/harmonic lock removal assist. Index Terms-stuck lock, harmonic lock, delay-locked loops, multi phase, phase detector, frequency synthesis

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-mu m CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

Effect of ambient on the resistance fluctuations of graphene

In this letter, we present the results of systematic experimental investigations of the effect of different chemical environments on the low frequency resistance fluctuations of single layer graphene field effect transistors. The shape of the power spectral density of noise was found to be determined by the energetics of the adsorption-desorption of molecules from the graphene surface making it the dominant source of noise in these devices. We also demonstrate a method of quantitatively determining the adsorption energies of chemicals on graphene surface based on noise measurements. We find that the magnitude of noise is extremely sensitive to the nature and amount of the chemical species present. We propose that a chemical sensor based on the measurement of low frequency resistance fluctuations of single layer graphene field effect transistor devices will have extremely high sensitivity, very high specificity, high fidelity, and fast response times. (c) 2015 AIP Publishing LLC.

A 0.5-2.0 GHz injection locked oscillator cascade for parallel wideband RF spectrum sensing

An area-efficient, wideband RF frequency synthesizer, which simultaneously generates multiple local oscillator (LO) signals, is designed. It is suitable for parallel wideband RF spectrum sensing in cognitive radios. The frequency synthesizer consists of an injection locked oscillator cascade (ILOC) where all the LO signals are derived from a single reference oscillator. The ILOC is implemented in a 130-nm technology with an active area of . It generates 4 uniformly spaced LO carrier frequencies from 500 MHz to 2 GHz. This design is the first known implementation of a CMOS based ILOC for wide-band RF spectrum sensing applications.