RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Memory Architecture Exploration Framework for Cache Based Embedded SoC

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences critical system design objectives like area, power and performance. Hence the embedded system designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

In this paper we propose the architecture of a SoC fabric onto which applications described in a HLL are synthesized. The fabric is a homogeneous layout of computation, storage and communication resources on silicon. Through a process of composition of resources (as opposed to decomposition of applications), application specific computational structures are defined on the fabric at runtime to realize different modules of the applications in hardware. Applications synthesized on this fabric offers performance comparable to ASICs while retaining the programmability of processing cores. We outline the application synthesis methodology through examples, and compare our results with software implementations on traditional platforms with unbounded resources.

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

System-level SoC near-field (NF) emissions: Simulation to measurement correlation

As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

Self-organized criticality in dynamics without branching

We demonstrate the phenomenon of self-organized criticality (SOC) in a simple random walk model described by a random walk of a myopic ant, i.e., a walker who can see only nearest neighbors. The ant acts on the underlying lattice aiming at uniform digging, i.e., reduction of the height profile of the surface but is unaffected by the underlying lattice. In one, two, and three dimensions we have explored this model and have obtained power laws in the time intervals between consecutive events of "digging." Being a simple random walk, the power laws in space translate to power laws in time. We also study the finite size scaling of asymptotic scale invariant process as well as dynamic scaling in this system. This model differs qualitatively from the cascade models of SOC.

Axially Loaded Timoshenko Rotors From A Prestressed Continuum Approach

We consider an axially loaded Timoshenko rotor rotating at a constant speed and derive its governing equations from a continuum viewpoint. The primary aim of this paper is to understand the source and role of gyroscopic terms, when the rotor is viewed not as a Timoshenko beam but as a genuine 3D continuum. We offer the primary insight that macroscopically observed gyroscopic terms may also, quite equivalently, be viewed as external manifestations of internally existing spin-induced prestresses at the continuum level. To demonstrate this idea with an analytical example (the Timoshenko rotor), we have studied the reliable equations of Choi et al. (Journal of Vibration and Acoustics, 114, 1992, 249-259). Using a straightforward application of our insight in the framework of nonlinear elasticity, we obtain equations that exactly match Choi et al. for the case with no axial load. For the case of axial preload, our straightforward formulation leads to a slightly different set of equations that have negligible numerical consequence for solid rotors. However, we offer a macroscopic, intuitive, justification for modifying our formulation so as to obtain the exact equations of Choi et al. with the axial load included.

Infinite Dimensional Slow Modulations In A Delayed Model For Orthogonal Cutting Vibrations

We apply the method of multiple scales (MMS) to a well known model of regenerative cutting vibrations in the large delay regime. By ``large'' we mean the delay is much larger than the time scale of typical cutting tool oscillations. The MMS upto second order for such systems has been developed recently, and is applied here to study tool dynamics in the large delay regime. The second order analysis is found to be much more accurate than first order analysis. Numerical integration of the MMS slow flow is much faster than for the original equation, yet shows excellent accuracy. The main advantage of the present analysis is that infinite dimensional dynamics is retained in the slow flow, while the more usual center manifold reduction gives a planar phase space. Lower-dimensional dynamical features, such as Hopf bifurcations and families of periodic solutions, are also captured by the MMS. Finally, the strong sensitivity of the dynamics to small changes in parameter values is seen clearly.

Speeding up AdaBoost Classifier with Random Projection

The development of techniques for scaling up classifiers so that they can be applied to problems with large datasets of training examples is one of the objectives of data mining. Recently, AdaBoost has become popular among machine learning community thanks to its promising results across a variety of applications. However, training AdaBoost on large datasets is a major problem, especially when the dimensionality of the data is very high. This paper discusses the effect of high dimensionality on the training process of AdaBoost. Two preprocessing options to reduce dimensionality, namely the principal component analysis and random projection are briefly examined. Random projection subject to a probabilistic length preserving transformation is explored further as a computationally light preprocessing step. The experimental results obtained demonstrate the effectiveness of the proposed training process for handling high dimensional large datasets.

Trehalose Toxicity in Cuscuta refexal Correlation With low Trehalase Activity

A toxic effect of a,a-trehalose in an angiospermic plant, Cuscuta reflexa (dodder), Is described. This disaccharide and Its analogs, 2-aminotrehalose and 4-aminotbhakose, induced a raid blackening of the terminal region of the vine which is Involved in elongation growth. From the results of in vitro growth of several angkiopermic plants and determination of trehalase activity in them, it is concluded that the toxic effect of trehalose in Cucaa is because of the very low trehalas activity In the vine. As a result, trehalose accumulates In the vine and interferes with some process closely associated with growth. The growth potential of Lemma (a duckweed) in a medium containing trehalose as the carbon source was ihreversibly lost upon addition of trealosamine, an Inhibitor of trehalase activity. It is concluded that, if allowed to accumulate within the tissue, trehalose may be potentiaMly toxic or inhibitory to higher plants in generaL The presence of trhalase actvity in plants, where Its substrate has not been found to occur, is envisged to relieve the plant from the toxic effects of trehalose which it may encounter in soil or during association with fungi or insects.

Structural Response of Partially Fibrous Concrete Beams

The inclusion of fibers into a matrix over only a partial thickness of the beam is regarded as partially fiber reinforcing a beam. This concept is fully invoked in the present investigation. A tensile strain enhancement factor, t, as determined by a direct tension test, forms a convenient engineering parameter that takes care of the influence of the aspect ratio and volume fraction of the given type of fiber. The appropriate thickness of the beam section to be reinforced with fibers is computed using the above parameter. Necessary analytical expressions were developed to compute the moment enhancement factor associated with different values of the parameter, t. The validity of the approach was experimentally demonstrated. Practically similar deflection patterns for fully and partially fibrous sections were observed. The applicability of the method developed in practical situations, such as the design of airfield and highway pavements with fiber conretes, is cited.

Studies of Phosphazenes. Part 13.' Thermal Rearrangement Reactions of Some Met hoxycyclo phosp hazenes

The methoxycyclophosphazenes [NP(OMe),], (n = 3-6) rearrange on heating to give oxocyclophosphazanes, [N(Me)PO(OMe)],. Isomeric products are formed when n = 4-6. The lH, ,lP, and 13C n.m.r. data for the starting materials and the products are presented. The ethoxy- and n-propoxy-derivatives N,P,( OR)* do not undergo the above rearrangement. The geminal derivatives N,P,R,(OMe), (R = Ph or NHBut) on heating yield both fully and partially rearranged products, namely dioxophosphaz-1 -enes and oxophosphazadienes, as shown by 270- MHz lH n.m.r. spectroscopy. The non-geminal derivative N,P,( NMe,),(OMe), gives only the fully rearranged product N,Me,P,(NMe,),O,(OMe), whose structure has been established from its lH and 31P n.m.r. spectra.