Quaternary adder, subtractor and multiplier using quaternary multiplexer

Multiplexers, as in the case of binary, are very useful building blocks in the development of quaternary systems. The use of quaternary multiplexer (QMUX) in the implementation of quaternary adder, subtractor and multiplier is described in this paper. Quaternary coded decimal (QCD) adder/subtractor and quaternary excess-3 adder/subtractor realization using QMUX are also proposed

A high gain aluminium electron multiplier

A twenty stage electron multiplier using aluminium as dynode material is described. When operated in DC mode, very stable gains approaching 106 were obtained with input currents of the order of 10-12 A, even after repeated exposures to the atmospheres.

A multiplier theorem for the sublaplacian on the Heisenberg group

A multiplier theorem for the sublaplacian on the Heisenberg group is proved using Littlewood-Paley-Stein theory of g-functions.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Theoretical Maximum Limits on Power-Handling Capacity of HVDC Cables

In the case of an ac cable, power transmission is limited by the length of the cable due to the capacitive reactive current component. It is well known that high-voltage direct current (HVDC) cables do not have such limitations. However, insulation-related thermal problems pose a limitation on the power capability of HVDC cables. The author presents a viable theoretical development, a logical extension to Whitehead's theory on thermal limitations of the insulation. The computation of the maximum power-carrying capability of HVDC cables subject to limits on the maximum operable temperature of the insulation is presented. The limitation on the power-carrying capability is closely associated with the electrothermal insulation failure. The effect of environmental interaction by way of external thermal resistance, an important aspect, is also considered in the formulations. The Lagrange multiplier method has been used to handle the ensuing optimization problem. The theory is based on an accepted theory of thermal breakdown in insulation and is an important and a coherent extension of great significance.

L2-stability of nonstationary feedback systems: Frequency-domain criteria

A frequency-domain positivity condition is derived for linear time-varying operators in2and is used to develop2stability criteria for linear and nonlinear feedback systems. These criteria permit the use of a very general class of operators in2with nonstationary kernels, as multipliers. More specific results are obtained by using a first-order differential operator with a time-varying coefficient as multiplier. Finally, by employing periodic multipliers, improved stability criteria are derived for the nonlinear damped Mathieu equation with a forcing function.

Multipliers of Sobolev spaces

Let Wm,p denote the Sobolev space of functions on Image n whose distributional derivatives of order up to m lie in Lp(Image n) for 1 less-than-or-equals, slant p less-than-or-equals, slant ∞. When 1 < p < ∞, it is known that the multipliers on Wm,p are the same as those on Lp. This result is true for p = 1 only if n = 1. For, we prove that the integrable distributions of order less-than-or-equals, slant1 whose first order derivatives are also integrable of order less-than-or-equals, slant1, belong to the class of multipliers on Wm,1 and there are such distributions which are not bounded measures. These distributions are also multipliers on Lp, for 1 < p < ∞. Moreover, they form exactly the multiplier space of a certain Segal algebra. We have also proved that the multipliers on Wm,l are necessarily integrable distributions of order less-than-or-equals, slant1 or less-than-or-equals, slant2 accordingly as m is odd or even. We have obtained the multipliers from L1(Image n) into Wm,p, 1 less-than-or-equals, slant p less-than-or-equals, slant ∞, and the multiplier space of Wm,1 is realised as a dual space of certain continuous functions on Image n which vanish at infinity.

Construction of Stability Multipliers with Prescribed Phase Characteristics: an Improved Value for $\sigma

For a feedback system consisting of a transfer function $G(s)$ in the forward path and a time-varying gain $n(t)(0 \leqq n(t) \leqq k)$ in the feedback loop, a stability multiplier $Z(s)$ has been constructed (and used to prove stability) by Freedman [2] such that $Z(s)(G(s) + {1 / K})$ and $Z(s - \sigma )(0 < \sigma < \sigma _ * )$ are strictly positive real, where $\sigma _ * $ can be computed from a knowledge of the phase-angle characteristic of $G(i\omega ) + {1 / k}$ and the time-varying gain $n(t)$ is restricted by $\sigma _ * $ by means of an integral inequality. In this note it is shown that an improved value for $\sigma _ * $ is possible by making some modifications in his derivation. ©1973 Society for Industrial and Applied Mathematics.

The averaging principle and the diagram technique

Rae and Davidson have found a striking connection between the averaging method generalised by Kruskal and the diagram technique used by the Brussels school in statistical mechanics. They have considered conservative systems whose evolution is governed by the Liouville equation. In this paper we have considered a class of dissipative systems whose evolution is governed not by the Liouville equation but by the last-multiplier equation of Jacobi whose Fourier transform has been shown to be the Hopf equation. The application of the diagram technique to the interaction representation of the Jacobi equation reveals the presence of two kinds of interactions, namely the transition from one mode to another and the persistence of a mode. The first kind occurs in the treatment of conservative systems while the latter type is unique to dissipative fields and is precisely the one that determines the asymptotic Jacobi equation. The dynamical equations of motion equivalent to this limiting Jacobi equation have been shown to be the same as averaged equations.

Construction of stability multipliers for non-linear feedback systems

This paper is concerned with the analysis of the absolute stability of a non-linear autonomous system which consists of a single non-linearity belonging to a particular class, in an otherwise linear feedback loop. It is motivated from the earlier Popovlike frequency-domain criteria using the ' multiplier ' eoncept and involves the construction of ' stability multipliers' with prescribed phase characteristics. A few computer-based methods by which this problem can be solved are indicated and it is shown that this constitutes a stop-by-step procedure for testing the stability properties of a given system.

Quadrature generation techniques for frequency multiplication based oscillators

Frequency multiplication (FM) can be used to design low power frequency synthesizers. This is achieved by running the VCO at a much reduced frequency, while employing a power efficient frequency multiplier, and also thereby eliminating the first few dividers. Quadrature signals can be generated by frequency- multiplying low frequency I/Q signals, however this also multiplies the quadrature error of these signals. Another way is generating additional edges from the low-frequency oscillator (LFO) and develop a quadrature FM. This makes the I-Q precision heavily dependent on process mismatches in the ring oscillator. In this paper we examine the use of fewer edges from LFO and a single stage polyphase filter to generate approximate quadrature signals, which is then followed by an injection-locked quadrature VCO to generate high- precision I/Q signals. Simulation comparisons with the existing approach shows that the proposed method offers very good phase accuracy of 0.5deg with only a modest increase in power dissipation for 2.4 GHz IEEE 802.15.4 standard using UMC 0.13 mum RFCMOS technology.

Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

A simple analog controller for single-phase half-bridge rectifier and its application to transformerless UPS

A simple, low-cost, constant frequency, analog controller is proposed for the front-end half-bridge rectifier of a single-phase transformerless UPS system to maintain near unity power factor at the input and zero dc-offset voltage at the output. The controller generates the required gating pulses by comparing the input current with a periodic, bipolar, linear carrier without sensing the input voltage. Two voltage controllers and a single integrator with reset are used to generate the required carrier. All the necessary control operations can be performed without using any PLL, multiplier and/or divider. The controller can be fabricated as a single integrated circuit. The control concept is validated through simulation and also experimentally on an 800W half-bridge rectifier. Experimental results are presented for ac-dc application, and also for ac-dc-ac UPS application with both sinusoidal and nonlinear loads. The simulation and experimental results agree well.