Nessy 7.0: entorno de inyección de fallos para Artix-7

El hardware reconfigurable es una tecnología emergente en aplicaciones espaciales.Debido a las características de este hardware, pues su configuración lógica queda almacenada en memoria RAM estática, es susceptible de diversos errores que pueden ocurrir con mayor frecuencia cuando es expuesta a entornos de mayor radiación, como en misiones de exploración espacial. Entre estos se encuentran los llamados SEU o Single Event Upset, y suelen ser generados por partículas cósmicas, pues pueden tener la capacidad de descargar un transistor y de este modo alterar un valor lógico en memoria, y por tanto la configuración lógica del circuito. Por ello que surge la necesidad de desarrollar técnicas que permitan estudiar las vulnerabilidades de diversos circuitos, de forma económica y rápida, además de técnicas de protección de los mismos. En este proyecto nos centraremos en desarrollar una herramienta con este propósito, Nessy 7.0. La plataforma nos permitirá emular, detectar y analizar posibles errores causados por la radiación en los sistemas digitales. Para ello utilizaremos como dispositivo controlador, una Raspberry Pi 3, que contendrá la herramienta principal, y controlará y se comunicará con la FPGA que implementará el diseño a testear, en este caso una placa Nexys 4 DDR con una FPGA Artix-7. Finalmente evaluaremos un par de circuitos con la plataforma.

Comparación de dos métodos de escritura de historia clínica electrónica

La historia clínica electrónica se ha convertido actualmente en el elemento fundamental de los sistemas de documentación clínica. Con el paso de los años se han producido grandes avances en las tecnologías de los sistemas de información electrónica que han mejorado la capacidad de almacenamiento, de procesamiento y de representación de la información clínica. Sin embargo, uno de los principales problemas de registro electrónico sigue siendo mejorar la eficiencia de estos sistemas a la hora de introducir los datos de salud de los pacientes. Este trabajo pretende comparar la eficiencia de estos sistemas en la gestión diaria de una consulta monográfica de Suelo Pélvico en un Servicio de Medicina Física y Rehabilitación...

Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs from MCUs

Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

A Methodology to Emulate Single Event Upsets in Flip-Flops using FPGAs through Partial Reconfiguration and Instrumentation

This paper presents a methodology to emulate Single Event Upsets (SEUs) in FPGA flip-flops (FFs). Since the content of a FF is not modifiable through the FPGA configuration memory bits, a dedicated design is required for fault injection in the FFs. The method proposed in this paper is a hybrid approach that combines FPGA partial reconfiguration and extra logic added to the circuit under test, without modifying its operation. This approach has been integrated into a fault-injection platform, named NESSY (Non intrusive ErrorS injection SYstem), developed by our research group. Finally, this paper includes results on a Virtex-5 FPGA demonstrating the validity of the method on the ITC’99 benchmark set and a Feed-Forward Equalization (FFE) filter. In comparison with other approaches in the literature, this methodology reduces the resource consumption introduced to carry out the fault injection in FFs, at the cost of adding very little time overhead (1.6 �μs per fault).

Hardware Implementation of a Fault-Tolerant Hopfield Neural Network on FPGAs

This letter presents an FPGA implementation of a fault-tolerant Hopfield NeuralNetwork (HNN). The robustness of this circuit against Single Event Upsets (SEUs) and Single Event Transients (SETs) has been evaluated. Results show the fault tolerance of the proposed design, compared to a previous non fault- tolerant implementation and a solution based on triple modular redundancy (TMR) of a standard HNN design.

A Study of the Robustness Against SEUs of Digital Circuits Implemented with FPGA DSPs

In this paper we present an experimental validation of the reliability increase of digital circuits implemented in XilinxTMFPGAs when they are implemented using the DSPs (Digital Signal Processors) that are available in the reconfigurable device. For this purpose, we have used a fault-injection platform developed by our research group, NESSY [1]. The presented experiments demonstrate that the probability of occurrence of a SEU effect is similar both in the circuits implemented with and without using embedded DSPs. However, the former are more efficient in terms of area usage, which leads to a decrease in the probability of a SEU occurrence.