A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

An adaptive frequency synthesizer architecture reducing reference sidebands

An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.

Phase-locked ring-defect photonic crystal vertical-cavity surface-emitting laser

Phase-locked oxide-confined ring-defect photonic crystal vertical-cavity surface-emitting laser is presented. The coupled-mode theory is employed to illustrate the two supermodes of the device, in-phase and out-of-phase supermode. Experimental results verify the two supermodes by the characteristics of the spectra and the far field patterns. At the lower current, only the out-of-phase supermode is excited, whereas under the higher current, the in-phase supermode also appears at the shorter wavelength range. In addition, the measured spectral separation between the two supermodes agrees well with the theoretical result.

Mechanisms of optical confinement in phase-locked laser arrays

The nature of optical confinement in phase-locked laser arrays (PLLAs) with a mesa-stripe structure (MSS) has been studied. Two main mechanisms are distinguished, which are based on the variation of the waveguide effective refractive index due to MSS formation and on the refractive index modulation induced by the heating of the structure. Stable operation was achieved when either weak or strong optical coupling was realized in the PLLA. A phase-locked regime of radiation was obtained only for laser diodes with strong optical coupling. In the latter case the angle divergency was not greater than 2 degrees for the antisymmetric supermode emission from the PLLA.

Microwave generation in an electro-absorption modulator integrated with a DFB laser subject to optical injection

This paper presents a new technique to generate microwave signal using an electro-absorption modulator (EAM) integrated with a distributed feedback (DFB) laser subject to optical injection. Experiments show that the frequency of the generated microwave can be tuned by changing the wavelength of the external laser or adjusting the bias voltage of the EAM. The frequency response of the EAM is studied and found to be unsmooth due to packaging parasitic effects and four-wave mixing effect occurring in the active layer of the DFB laser. It is also demonstrated that an EA modulator integrated in between two DFB lasers can be used instead of the EML under optical injection. This integrated chip can be used to realize a monolithically integrated tunable microwave source. (C) 2009 Optical Society of America

Phase locking of fibre lasers by self-imaging resonator

Experimental demonstrations of the use of a self-imaging resonator in the phase locking of two fibre lasers are presented. The output power of the phase-locked fibre laser array exceeded 2 W Successful attempts of phase locking show that the fibre laser array is not only capable of producing high Output Power but also large on-axis intensity by this method.

星间相干光通信中的光学锁相环

在相干体制下,二进制相移键控(BPSK)信号调制的零差接收机可实现理论上的最高灵敏度,是星间相干光通信的研究和应用重点。零差接收机要求本振波和信号波严格相位同步,常用的相位同步技术是光学锁相环(OPLL)。阐述了光学锁相环的基本原理,介绍了近20年来光学锁相环的发展,在此基础上总结了各种类型锁相环的性能和适用范围。回顾了欧洲国家在星间相干光通信计划中通信终端使用光学锁相环的情况。最后对光学锁相环技术进行了总结,对该技术的前景进行了展望。

两根掺镱大芯双包层光纤激光器获得113W同相输出功率

利用一个自成像共焦腔和一个空间滤波器实现了两掺Yb大芯光纤激光器的位相锁定。观测到稳定的具有高对比度的干涉条纹。相干条纹的对比度为59%，而非相干时对比度为6%。中心条纹的宽度与理论计算结果吻合得很好。对同相模式而言，位相锁定激光器阵列输出达到113W，对应的斜率效率为38.5%。

Beam combination of a radial laser array: Flat-topped beam

An analytical expression of a radial laser array for flat-topped beam is derived based on the generalized Collins formula. The intensity distribution of the resulting beam focused by a lens at the focus plane, for phase-locked and nonphase-locked cases, is studied numerically. The effect of the Fresnel number and normalized radius on intensity distribution for phase-locked and nonphase-locked cases is also presented. It is found that intensity distribution for nonphase-locked case is much less sensible to the Fresnel number and normalized radius than that of phase-locked case. (C) 2008 Elsevier Ltd. All rights reserved.

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.

Anti-cyclonic eddies northwest of Luzon in summer-fall observed by satellite altimeters

Anti-cyclonic eddies northwest of Luzon of the Philippines in summer-fall are identified in the merged data products of satellite altimeters of Topex/Poseidon, Jason-1 and European Research Satellites. The generation and propagation of the anti-cyclonic eddies, which are confirmed by satellite ocean color data, are found to be a seasonal phenomenon that is phase-locked to the onset of the southwesterly monsoon and the relaxation of the cyclonic wind curl in the northeastern South China Sea. The eddies originate from northwest of Luzon in summer, move across the northeastern South China Sea to reach the China continental slope in fall, and propagate southwestward along the continental slope in fall-winter, inducing shelfbreak current variations in the western South China Sea in fall-winter. The anti-cyclonic eddy discovered by Li et al. (1998) in the northern South China Sea is found to originate from northwest of Luzon and carry primarily the South China Sea waters. It does not appear to be an eddy shed from the Kuroshio in the Luzon Strait area as alluded by Li et al. (1998) and others.