A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

On-Chip All-Optical Passive 3.55 Gbit/s NRZ-to-PRZ Format Conversion Using a High-Q Silicon-Based Microring Resonator

We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108 ps width and 4.98 dB ER.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

Sub-nanosecond silicon-on-insulator optical micro-ring switch with low crosstalk

We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator (SOI) dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-mu m-radius micro-ring with the well-designing asymmetric dual-coupling structure. By optimizations of the doping profiles and the fabrication processes, the sub-nanosecond switch-on/off time of < 400 ps is finally realized under an electrical pre-emphasized driving signal. This compact and fast-response micro-ring switch, which can be fabricated by complementary metal oxide semiconductor (CMOS) compatible technologies, have enormous potential in optical interconnects of multicore networks-on-chip.

Fabrication of triplexers based on flattop SOI AWG

A triplexer is fabricated based on SOI arrayed waveguide gratings (AWGs). Three wavelengths of the triplexer operate at different diffraction orders of an arrayed waveguide grating. The signals of 1490 nm and 1550 nm, which are input from central input waveguide of an AWG, are demultiplexed and the signal of 1310 nm, which is input from central output waveguide of an AWG, is uploaded. The tested results show that the downloaded and uploaded signals have flat-top response. The insertion loss is 9 dB on chip, the nonadjacent crosstalk is less than -30 dB for 1490 nm and 1301 nm, and is less than -25 dB for 1550 nm, the 3 dB bandwidth equates that of the input light source.

Monolithic optical gates based on integration of evanescently-coupled uni-traveling-carrier photodiodes and electroabsorption modulators

We report on chip-scale optical gates based on the integration of evanescent waveguide unitraveling-carrier photodiodes (EC-UTC-PDs) and intra-step quantum well electroabsorption modulators (IQW-EAMs) on n-InP substrates. These devices exhibit simultaneously 2.1 GHz and -16.2 dB RF-gain at 21 GHz with a 450 Omega thin-film resistor and a bypass capacitor integrated on a chip.

Real-time data processing of interferential imaging spectrometer based on FPGA

Based on the data processing technologies of interferential spectrometer, a sort of real-time data processing system on chip of interferential imaging spectrometer was studied based on large capacitance and high speed field programmable gate array( FPGA) device. The system integrates both interferograrn sampling and spectrum rebuilding on a single chip of FPGA and makes them being accomplished in real-time with advantages such as small cubage, fast speed and high reliability. It establishes a good technical foundation in the applications of imaging spectrometer on target detection and recognition in real-time.

Electrochemical detector based on sol-gel-derived carbon composite material for capillary electrophoresis microchips

An on-chip disk electrode based on sol-gel-derived carbon composite material could be easily and reproducibly fabricated. Unlike other carbon-based electrodes reported previously, this detector is rigid, convenient to fabricate, and amenable to chemical modifications. Based on the stable and reproducible characters of this detector, a copper particle-modified detector was developed for the detection of carbohydrates which extends the application of the carbon-based electrode. In our experiments, the performance of the new integrated detector for rapid on-chip measurement of epinephrine and glucose was illustrated. Experimental procedures including the fabrication of this detector, the configuration of separation channel outlet and electrode verge, and the performance characteristics of this new electrochemical detector were investigated.

Compact SOI arrayed waveguide grating demultiplexer with broad spectral response

A compact eight-channel flat spectral response arrayed waveguide grating (AWG) multiplexer based on siliconon-insulator (SOI) materials has been fabricated on the planar lightwave circuit (PLC). The 1-dB bandwidth of 48 GHz and 3-dB bandwidth of 69 GHz are obtained for the 100 GHz channel spacing. Not only non-adjacent crosstalk but also adjacent crosstalk are less than -25 dB. The on-chip propagation loss range is from 3.5 to 3.9 dB, and the 2 total device size is 1.5 x 1.0 cm(2). (c) 2005 Elsevier B.V. All rights reserved.

A 5.6-mW Power Dissipation CMOS Frequency Synthesizer for L1/L2 Dual-Band GPS Application

This paper presents a wide tuning range CMOS frequency synthesizer for dual-band GPS receiver, which has been fabricated in a standard 0.18-um RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45GHz and 3.14GHz in case of process corner or temperature variation, with a current consumption varying accordingly from 0.8mA to 0.4mA, from a 1.8V supply voltage. The measurement results show that the whole frequency synthesizer costs a very low power consumption of 5.6mW working at L I band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112 dBc/Hz at 1MHz offset from a 3.142GHz carrier.

A widely tunable continuous-time LPF for a direct conversion DBS Tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in a 0.35um SiGe BiCMOS technology. The filter's -3dB cutoff frequency f(0) can be tuned from 4MHz to 40MHz. A novel translinear transconductor (Gm) cell is used to implement the widely tunable and high linear filter. The filter has -0.5dB passband gain, 28nV/Hz(1/2) input referred noise, -2dBVrms passband IIP3, 24dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 16mA (with f(0)=20MHz) from 3.3 V supply, and occupy an area of 0.45 mm(2).

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz~(1/2) input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f_0 = 20 MHz) from 5 V supply, and occupy 0.5 mm~2.