Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Properties of high k gate dielectric gadolinium oxide deposited on Si(100) by dual ion beam deposition (DIBD)

Gadolinium oxide thin films have been prepared on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Substrate temperature was an important factor to affect the crystal structures and textures in an ion energy range of 100-500 eV. The films had a monoclinic Gd2O3 structure with preferred orientation ((4) over bar 02) at low substrate temperatures. When the substrate temperature was increased, the orientation turned to (202), and finally, the cubic structure appeared at the substrate temperature of 700 degreesC, which disagreed with the previous report because of the ion energy. The AES studies found that Gadolinium oxide shared Gd2O3 structures, although there were a lot of oxygen deficiencies in the films, and the XPS results confirmed this. AFM was also used to investigate the surface images of the samples. Finally, the electrical properties were presented. (C) 2004 Elsevier B.V. All rights reserved.

Development of high-k gate dielectric materials

The traditional gate dielectric material Of SiO2 can not satisfy the need of the continuous downscaling of CMOS dimensions. High-K gate dielectric materials have attracted extensive research efforts recently and obtained great progress. In this paper, the developments of high-K gate materials were reviewed. Based on the author's background and research work in the area, the latest achievements of high-K gate dielectric materials on the recrystalization temperature, the low-K interface layer, and the dielectric breakdown and metal gate electrode were introduced in detail.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

High-performance 2 mm gate width GaNHEMTs on 6H-SiC with output power of 22.4 W @ 8 GHz

Optimized AlGaN/AlN/GaN high electron mobility transistors (HEMTs) structures were grown on 2-in semi-insulating (SI) 6H-SiC substrate by metal-organic chemical vapor deposition (MOCVD). The 2-in. HEMT wafer exhibited a low average sheet resistance of 305.3 Omega/sq with a uniformity of 3.85%. The fabricated large periphery device with a dimension of 0.35 pm x 2 nun demonstrated high performance, with a maximum DC current density of 1360 mA/mm, a transconductance of 460 mS/mm, a breakdown voltage larger than 80 V, a current gain cut-off frequency of 24 GHz and a maximum oscillation frequency of 34 GHz. Under the condition of continuous-wave (CW) at 9 GHz, the device achieved 18.1 W output power with a power density of 9.05 W/mm and power-added-efficiency (PAE) of 36.4%. While the corresponding results of pulse condition at 8 GHz are 22.4 W output power with 11.2 W/mm power density and 45.3% PAE. These are the state-of-the-art power performance ever reported for this physical dimension of GaN HEMTs based on SiC substrate at 8 GHz. (c) 2008 Elsevier Ltd. All rights reserved.

Role of interface dipole in metal gate/high-k effective work function modulation by aluminum incorporation

The interface dipole and its role in the effective work function (EWF) modulation by Al incorporation are investigated. Our study shows that the interface dipole located at the high-k/SiO2 interface causes an electrostatic potential difference across the metal/high-k interface, which significantly shifts the band alignment between the metal and high-k, consequently modulating the EWF. The electrochemical potential equalization and electrostatic potential methods are used to evaluate the interface dipole and its contribution. The calculated EWF modulation agrees with experimental data and can provide insight to the control of EWF in future pMOS technology.

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

Properties of high k gate dielectric gadolinium oxide deposited on Si(100) by dual ion beam deposition (DIBD)

Gadolinium oxide thin films have been prepared on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Substrate temperature was an important factor to affect the crystal structures and textures in an ion energy range of 100-500 eV. The films had a monoclinic Gd2O3 structure with preferred orientation ((4) over bar 02) at low substrate temperatures. When the substrate temperature was increased, the orientation turned to (202), and finally, the cubic structure appeared at the substrate temperature of 700 degreesC, which disagreed with the previous report because of the ion energy. The AES studies found that Gadolinium oxide shared Gd2O3 structures, although there were a lot of oxygen deficiencies in the films, and the XPS results confirmed this. AFM was also used to investigate the surface images of the samples. Finally, the electrical properties were presented. (C) 2004 Elsevier B.V. All rights reserved.

Broadband polarization-insensitive semiconductor optical amplifier gate with tensile InGaAs quasi-bulk and compressively strained InGaAs wells

A novel wideband polarization-insensitive semiconductor optical amplifier (SOA) gate containing compressively strained InGaAs quantum wells and tensile-strained InGaAs quasi-bulk layers is developed. The fabricated SOA gates have a wide 3-dB optical bandwidth of 102 nm, less than 0.8-dB polarization sensitivity, more than 50-dB extinction ratio, and less than 75-mA fiber-to-fiber lossless operating current. (C) 2004 Society of Photo-Optical Instrumentation Engineers.

ac gate-induced Fano resonance and peak splitting of conductance in a quantum dot

We have investigated the conductance of a quantum dot system suffering an anti-symmetric ac gate voltage which induces the transition between dot levels in the linear regime at zero temperature in the rotating wave approximation. Interesting Fano resonances appear on one side of the displaced resonant tunnelling peaks for the nonresonant case or the peak splitting for the resonant case. The line shape of conductance (vs Fermi energy) near each level of the quantum dot can be decomposed into two profiles: a Breit-Wigner peak and a Fano profile, or a Breit-Wigner peak and a dip in both cases.

Theoretical analysis of gate voltage-controlled subband states in an AlxGa1-xN/GaN heterostructure

The subband structure and inter-subband transition as a function of gate voltage are determined by solving the Schrodinger and Poisson equations self-consistently in an AlxGa1-xN/GaN heterostructure. Different aluminum mole fraction and thickness of AlxGa1-xN barrier are considered. Calculation results show that energy difference between the first and second subband covers a wide range (from several tens to hundreds milli-electron volt) by applying different gate voltage, which corresponds to the midinfrared and long-wave infrared wavelength scope. Furthermore, such a modulation on the subband transition energy is much more pronounced for the structure with thin barrier. When the applied positive gate voltage is increased, the triangle well formed at the interface turns to be deeper and narrower, which enhances the confinement for electrons. As a result, the overlap between electron wave function at two subbands increases, and thus the optical intersubband transition also enhances its intensity. This tendency is in good agreement with the available data in the literature. (c) 2005 Elsevier B.V. All rights reserved.

Effect of the technology of implanting nitrogen into buried oxide on the radiation hardness of the top gate oxide for partially depleted SOIPMOSFET

The effect of implanting nitrogen into buried oxide on the top gate oxide hardness against total irradiation does has been investigated with three nitrogen implantation doses (8 x 10(15), 2 x 10(16) and 1 x 10(17) cm(-2)) for partially depleted SOI PMOSFET. The experimental results reveal the trend of negative shift of the threshold voltages of the studied transistors with the increase of nitrogen implantation dose before irradiation. After the irradiation with a total dose of 5 x 10(5) rad(Si) under a positive gate voltage of 2V, the threshold voltage shift of the transistors corresponding to the nitrogen implantation dose 8 x 10(15) cm(-2) is smaller than that of the transistors without implantation. However, when the implantation dose reaches 2 x 10(16) and 1 x 10(17) cm(-2), for the majority of the tested transistors, their top gate oxide was badly damaged due to irradiation. In addition, the radiation also causes damage to the body-drain junctions of the transistors with the gate oxide damaged. All the results can be interpreted by tracing back to the nitrogen implantation damage to the crystal lattices in the top silicon.

1-mm gate periphery AlGaN/AIN/GaN HEMTs on SiC with output power of 9.39 W at 8 GHz

AlGaN/AlN/GaN high electron mobility transistor (HEMT) structures with high mobility GaN channel layer were grown on 50 min diameter semi-insulating (SI) 6H-SiC substrates by metalorganic chemical vapor deposition and large periphery HEMT devices were fabricated and characterized. High two-dimensional electron gas mobility of 2215 cm(2)/V s at room temperature with sheet electron concentration of 1.044 x 10(13)/cm(2) was achieved. The 50 mm diameter HEMT wafer exhibited a low average sheet resistance of 251.0 Omega/square, with the resistance uniformity of 2.02%. Atomic force microscopy measurements revealed a smooth AlGaN surface with a root-mean-square roughness of 0.27 nm for a scan area of 5 mu mi x 5 pm. The 1-mm gate width devices fabricated using the materials demonstrated a very high continuous wave output power of 9.39 W at 8 GHz, with a power added efficiency of 46.2% and power gain of 7.54 dB. A maximum drain current density of 1300 mA/mm, an extrinsic transconductance of 382 mS/mm, a current gain cutoff frequency of 31 GHz and a maximum frequency of oscillation 60 GHz were also achieved in the same devices. (C) 2007 Elsevier Ltd. All rights reserved.

Growth and characterization of 0.8-mu m gate length AlGaN/GaN HEMTs on sapphire substrates

AlGaN/GaN high electron mobility transistor (HEMT) structures were grown on 2 inch sapphire substrates by MOCVD, and 0.8-mu m gate length devices were fabricated and measured. It is shown by resistance mapping that the HEMT structures have an average sheet resistance of approximately 380 Omega/sq with a uniformity of more than 96%. The 1-mm gate width devices using the materials yielded a pulsed drain current of 784 mA/mm at V-gs=0.5 V and V-ds=7 V with an extrinsic transconductance of 200 mS/mm. A 20-GHz unity current gain cutoff frequency (f(T)) and a 28-GHz maximum oscillation frequency (f(max)) were obtained. The device with a 0.6-mm gate width yielded a total output power of 2.0 W/mm (power density of 3.33 W/mm) with 41% power added efficiency (PAE) at 4 GHz.