Relay lens-free birefringence-customized stackable beam-steering modules for optical interconnects

A previously suggested birefringence-customized modular optical interconnect technique is extended for lens-free relay operation. Various lens-free relay imaging models are developed. We claim that the lens-free relay system is important in simplifying an optical interconnect system whenever the imaging conditions permit. To verify the validity of various proposed concepts, we experimentally implemented some 8 x 8 optical permutation modules. High-power efficiency and low channel cross talk were experimentally observed. In general, the larger the channel spacing, the less the cross talk. A quantitative cross-talk measurement of the lens-free relay system shows that, for a fixed channel width of 0.5 mm and channel spacings of 0.5, 1, and 2 mm, a less than -20-dB cross-talk performance can be guaranteed for lens-free relay distances of 40, 280, and 430 mm, respectively. (C) 1998 Optical Society of America.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz.

低β四分之一波长腔中的束流偏转的分析性研究(英文)；Analytical Study on Beam Steering in Low-β Superconducting Quarter Wave Resonators

目前加速速度范围在0.01c—0.3c的粒子的超导腔主要使用四分之一波长腔型。用于不同加速器上的频率范围在50—240MHz的四分之一波长腔在建造或者预研中。这种腔型的一个不足是其横向电磁成分会造成束流偏转效应,从而导致发射度的增长和束流的溢漏,在强流重离子加速器中这种效应尤为严重。对中国科学院近代物理研究所超导直线加速器中的频率为80.5和161MHz的四分之一波长腔的偏转效应进行了分析,计算结果表明,在四分之一腔体的设计时需要考虑到束流偏转的修正,这通常需要在漂移管端面上削适当大小的倾角来实现。

Synthesis of NaA zeolite membranes from clear solution

NaA zeolite membranes were successfully synthesized on a porous alpha -Al2O3 support from clear solution. The synthesis parameters, such as surface seeding, synthesis time, synthesis stages, etc. were investigated. Surface seeding can not only accelerate the formation of NaA zeolite on the support surface, but can also inhibit the transformation of NaA zeolite into other types of zeolites. A continuous NaA zeolite membrane formed on the seeded support after 2 h of synthesis. Gas permeation results showed that a synthesis time of 3 h produced the best NaA zeolite membrane. When the synthesis time was longer than 4 h, the NaA zeolite on the support surface began to transform into other types of zeolites, and the quality of the NaA zeolite membrane decreased. The quality of the NaA zeolite membrane can be improved by employing the multi-stage synthesis method. The NaA zeolite membrane with a synthesis time of 2 h after a two-stage synthesis showed the best gas permeation performance. The permeances of H-2, O-2, N-2, and n-C4H10 decreased as the molecular kinetic diameter of the gases increased. which showed the molecular sieving effect of the NaA zeolite membrane. The permselectivities of H-2/n-C4H10 and O-2/N-2 were 19.1 and 1.8, respectively. These values are higher than the Knudsen diffusion ratios of 5.39 and 0.94. However, the permeation of n-C4H10 also indicated that the NaA zeolite membrane had certain defects with diameters larger than the pore size of NaA zeolite. A synthesis model was proposed to clarify the effect of surface seeding. (C) 2001 Elsevier Science B.V. All rights reserved.