Performance of an embedded optical vector matrix multiplication processor architecture

An embedded architecture of optical vector matrix multiplier (OVMM) is presented. The embedded architecture is aimed at optimising the data flow of vector matrix multiplier (VMM) to promote its performance. Data dependence is discussed when the OVMM is connected to a cluster system. A simulator is built to analyse the performance according to the architecture. According to the simulation, Amdahl's law is used to analyse the hybrid opto-electronic system. It is found that the electronic part and its interaction with optical part form the bottleneck of system.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

High-Strength Composite Fibers: Realizing True Potential of Carbon Nanotubes in Polymer Matrix through Continuous Reticulate Architecture and Molecular Level Couplings

Carbon nanotubes have unprecedented mechanical properties as defect-free nanoscale building blocks, but their potential has not been fully realized in composite materials due to weakness at the interfaces. Here we demonstrate that through load-transfer-favored three-dimensional architecture and molecular level couplings with polymer chains, true potential of CNTs can be realized in composites as Initially envisioned. Composite fibers with reticulate nanotube architectures show order of magnitude improvement in strength compared to randomly dispersed short CNT reinforced composites reported before. The molecular level couplings between nanotubes and polymer chains results in drastic differences in the properties of thermoset and thermoplastic composite fibers, which indicate that conventional macroscopic composite theory falls to explain the overall hybrid behavior at nanoscale.

TWO-DIMENSIONAL ARRAY OF ION TRAPS ON A PLANAR CHIP

We investigate a planar ion chip design with a two-dimensional array of linear ion traps for the scalable quantum information processor. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate, a combination of appropriate rf and DC potentials are applied to them for stable ion confinement, and the trap axes are located above the surface at a distance controlled by the electrodes' lateral extent and the substrate's height as discussed. The potential distributions are calculated using static electric field qualitatively. This architecture is conceptually simple and many current microfabrication techniques are feasible for the basic structure. It may provide a promising route for scalable quantum computers.

MODIFIED DIRECT TWOS-COMPLEMENT PARALLEL ARRAY MULTIPLICATION ALGORITHM FOR COMPLEX MATRIX OPERATION

A direct twos-complement parallel array multiplication algorithm is introduced and modified for digital optical numerical computation. The modified version overcomes the problems encountered in the conventional optical twos-complement algorithm. In the array, all the summands are generated in parallel, and the relevant summands having the same weights are added simultaneously without carries, resulting in the product expressed in a mixed twos-complement system. In a two-stage array, complex multiplication is possible with using four real subarrays. Furthermore, with a three-stage array architecture, complex matrix operation is straightforwardly accomplished. In the experiment, parallel two-stage array complex multiplication with liquid-crystal panels is demonstrated.

Optical intrinsically fuzzy mathematical morphology for gray-scale image processing

Intrinsically fuzzy morphological erosion and dilation are extended to a total of eight operations that have been formulated in terms of a single morphological operation--biased dilation. Based on the spatial coding of a fuzzy variable, a bidirectional projection concept is proposed. Thus, fuzzy logic operations, arithmetic operations, gray-scale dilation, and erosion for the extended intrinsically fuzzy morphological operations can be included in a unified algorithm with only biased dilation and fuzzy logic operations. To execute this image algebra approach we present a cellular two-layer processing architecture that consists of a biased dilation processor and a fuzzy logic processor. (C) 1996 Optical Society of America

Visual pattern recognition network: Its training algorithm and its optoelectronic architecture

A visual pattern recognition network and its training algorithm are proposed. The network constructed of a one-layer morphology network and a two-layer modified Hamming net. This visual network can implement invariant pattern recognition with respect to image translation and size projection. After supervised learning takes place, the visual network extracts image features and classifies patterns much the same as living beings do. Moreover we set up its optoelectronic architecture for real-time pattern recognition. (C) 1996 Optical Society of America

Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (C) 1999 Optical Society of America.

Solid-state optical parallel morphological processor

Based on birefringence, a building-block stacking technique is suggested in this paper. A solid-state optical morphological processor module is thus developed, which is an integration of a beam array generator submodule, an optical connector submodule, and a Pockels readout optical modulator. It is shown that the technique is compact in construction, simple for fabrication, and insensitive to the environment.

Optoelectronic quotient-selected modified signed-digit division

A novel optoelectronic quotient-selected modified signed-digit division technique is proposed. This division method generates one quotient digit per iteration involving only one shift operation, one quotient selection operation and one addition/subtraction operation. The quotient digit can be selected by observing three most significant digits of the partial remainder independent of the divisor. Two algorithms based on truth-table look-up and binary logic operations are derived. For optoelectronic implementation, an efficient shared content-addressable memory based architecture as well as compact logic array processor based architecture with an electron-trapping device is proposed. Performance evaluation of the proposed optoelectronic quotient-selected division shows that it is faster than the previously reported convergence division approach. Finally, proof-of-principle experimental results are presented to verify the effectiveness of the proposed technique. (C) 2001 Society of Photo-Optical Instrumentation Engineers.