飞行高度及设计长度对锥形流乘波体优化的影响 Altitude and Design Length Effects of Optimized Waverider Derived from Cone Flow

高超声速条件下,乘波体布局具有高升阻比特性,本文应用单纯形加速法,以最大升阻比为目标,开展了锥形流乘波体布局优化设计研究.特别是,研究了在高层大气飞行时雷诺数效应与气动特性的关系,从乘波体飞行高度与设计长度两方面探讨雷诺数对乘波体优化的影响,结果表明：给定设计马赫数和圆锥角情况下,对于最大升阻比优化乘波体,其雷诺数越小,摩擦阻力越大,而升阻比越低.

Mode Analysis and Design of a Low-Loss Photonic Crystal 60 degrees Waveguide Bend

The guided modes of a two-dimensional photonic crystal straight waveguide and a waveguide bend are studied in order to find the high transmission mechanism for the waveguide bend. We find that high transmission occurs when the mode patterns and wave numbers match, while the single-mode condition in the waveguide bend is not necessarily required. According to the mechanism, a simply modified bend structure with broad high transmission band is proposed. The bandwidth is significantly increased from 19 to 116 nm with transmission above 90%, and covers the entire C band of optical communication.

On the performance analysis and design of a novel shared-layer integrated devices using RCE-p-i-n-PD/SHBT - art. no. 67820J

We have explored the shared-layer integration fabrication of an resonant-cavity-enhanced p-i-n photodector (RCE- p-i-n-PD) and a single heterojunction bipolar transistor (SHBT) with the same epitaxy grown layer structure. MOCVD growth of the different layer structure for the GaAs based RCE- p-i-n-PD/SHBT require compromises to obtain the best performance of the integrated devices. The SHBT is proposed with super-lattice in the collector, and the structure of the base and the collector of the SHBT is used for the RCE. Up to now, the DC characteristics of the integrated device have been obtained.

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

The effects of key geometrical parameters on the performance of integrated spiral inductors are investigated with the 3D electromagnetic simulator HFSS. While varying geometrical parameters such as the number of turns （N）,the width of the metal traces （W）,the spacing between the traces （S）,and the inner diameter （ID）, changes in the performance of the inductors are analyzed in detail. The reasons for these changes in performance are presented. Simulation results indicate that the performance of an integrated spiral inductor can be improved by optimizing its layout. Some design rules are summarized.

Design and Verification of the Programming Circuit in an Application-Specific FPGA

In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal. Even though our focus is on the programming circuitry that provides the interface between the FPGA core circuit and the external programming hardware, the parametrized design method can be generalized to the design of entire chip for all members in the FPGA family. The method presented here covers the generation of the design RTL files and the support files for synthesis, place-and-route layout and simulations. The proposed method is proven to work smoothly within the complete chip design methodology. We will describe the implementation of this method to the design of the programming circuit in details including the design flow from the behavioral-level design to the final layout as well as the verification. Different package options and different programming modes are included in the description of the design. The circuit design implementation is based on SMIC 0.13-micron CMOS technology.