Application of the Conjugate Gradient Optimization Algorithm of Neural Network on Laser Machining

在应用激光技术加工复杂曲面时,通常以采样点集为插值点来建立曲面函数,然后实现曲面上任意坐标点的精确定位。人工神经网络的BP算法能实现函数插值,但计算精度偏低,往往达不到插值精确要求,造成较大的加工误差。提出人工神经网络的共轭梯度最优化插值新算法,并通过实例仿真,证明了这种曲面精确定位方法的可行性,从而为激光加工的三维精确定位提供了一种良好解决方案。这种方法已经应用在实际中。

A Complex BPF with On Chip Auto-tuning Architecture for Wireless Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18um standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 16.2dBm, with 50 Omega as the source impedance. The input referred noise is about 80uV(rms). The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28 x 0.22 mm(2), less than 1/8 of that of the main-filter which is 0.92 x 0.59 mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Complex BPF with On Chip Auto-tuning Architecture for Low-IF Receivers

A 3(rd) order complex band-pass filter (BPF) with auto-tuning architecture is proposed in this paper. It is implemented in 0.18 mu m standard CMOS technology. The complex filter is centered at 4.092MHz with bandwidth of 2.4MHz. The in-band 3(rd) order harmonic input intercept point (IIP3) is larger than 19dBm, with 50 Omega as the source impedance. The input referred noise is about 80 mu V-rms. The RC tuning is based on Binary Search Algorithm (BSA) with tuning accuracy of 3%. The chip area of the tuning system is 0.28x0.22mm(2), less than 1/8 of that of the main-filter which is 0.92x0.59mm(2). After tuning is completed, the tuning system will be turned off automatically to save power and to avoid interference. The complex filter consumes 2.6mA with a 1.8V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

On-Chip All-Optical Passive 3.55 Gbit/s NRZ-to-PRZ Format Conversion Using a High-Q Silicon-Based Microring Resonator

We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108 ps width and 4.98 dB ER.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

Large-scale, uniform DNA network on 11-mercaptoundecanoic acid modified gold (111) surface: Atomic force microscopy study

Large-scale, uniform plasmid deoxyribonucleic acid (DNA) network has been successfully constructed on 11-mercaptoundecanoic acid modified gold (111) surface using a self-assembly technique. The effect of DNA concentration on the characteristics of the DNA network was investigated by atomic force microscopy. It was found that the size of meshes and the height of fibers in the DNA network could be controlled by varying the concentration of DNA with a constant time of assembly of 24 h.

High-frequency characterization of packaging network in to-can photodiode modules

A simple method for analyzing the effects of TO packaging network on the high-frequency response of photodiode modules is presented. This method is established based on the relations of the scattering parameters of the packaging network, photodiode chip, and module. It is shown that the results obtained by this method agree well with those obtained by the conventional comparison method. The proposed method is much more convenient since only the electrical domain measurements are required. (C) 2008 Wiley Periodicals, Inc.

Sub-nanosecond silicon-on-insulator optical micro-ring switch with low crosstalk

We demonstrate a sub-nanosecond electro-optical switch with low crosstalk in a silicon-on-insulator (SOI) dual-coupled micro-ring embedded with p-i-n diodes. A crosstalk of -23 dB is obtained in the 20-mu m-radius micro-ring with the well-designing asymmetric dual-coupling structure. By optimizations of the doping profiles and the fabrication processes, the sub-nanosecond switch-on/off time of < 400 ps is finally realized under an electrical pre-emphasized driving signal. This compact and fast-response micro-ring switch, which can be fabricated by complementary metal oxide semiconductor (CMOS) compatible technologies, have enormous potential in optical interconnects of multicore networks-on-chip.

Fabrication of triplexers based on flattop SOI AWG

A triplexer is fabricated based on SOI arrayed waveguide gratings (AWGs). Three wavelengths of the triplexer operate at different diffraction orders of an arrayed waveguide grating. The signals of 1490 nm and 1550 nm, which are input from central input waveguide of an AWG, are demultiplexed and the signal of 1310 nm, which is input from central output waveguide of an AWG, is uploaded. The tested results show that the downloaded and uploaded signals have flat-top response. The insertion loss is 9 dB on chip, the nonadjacent crosstalk is less than -30 dB for 1490 nm and 1301 nm, and is less than -25 dB for 1550 nm, the 3 dB bandwidth equates that of the input light source.

The design algorithm of an associative memory neural network

A design algorithm of an associative memory neural network is proposed. The benefit of this design algorithm is to make the designed associative memory model can implement the hoped situation. On the one hand, the designed model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. The result has improved the ones of some old associative memory neural network. On the other hand, the memory samples are in the centers of the fault-tolerant. In average significance the radius of the memory sample fault-tolerant field is maximum.

Potential frequency bandwidth estimation of TO packaging techniques for photodiode modules

Scattering parameters of photodiode chip, TO header and TO packaged module are measured, and the effects of TO packaging network on the high-frequency response of photodiode are investigated. Based on the analysis, the potential bandwidth of TO packaging techniques is estimated from the scattering parameters of the TO packaging network. Another method for estimating the potential bandwidth from the equivalent circuit for the TO packaged photodiode model is also presented. The results obtained using both methods show that the TO packaging techniques used in the experiments can potentially achieve a frequency bandwidth of 22 GHz.

Monolithic optical gates based on integration of evanescently-coupled uni-traveling-carrier photodiodes and electroabsorption modulators

We report on chip-scale optical gates based on the integration of evanescent waveguide unitraveling-carrier photodiodes (EC-UTC-PDs) and intra-step quantum well electroabsorption modulators (IQW-EAMs) on n-InP substrates. These devices exhibit simultaneously 2.1 GHz and -16.2 dB RF-gain at 21 GHz with a 450 Omega thin-film resistor and a bypass capacitor integrated on a chip.

Real-time data processing of interferential imaging spectrometer based on FPGA

Based on the data processing technologies of interferential spectrometer, a sort of real-time data processing system on chip of interferential imaging spectrometer was studied based on large capacitance and high speed field programmable gate array( FPGA) device. The system integrates both interferograrn sampling and spectrum rebuilding on a single chip of FPGA and makes them being accomplished in real-time with advantages such as small cubage, fast speed and high reliability. It establishes a good technical foundation in the applications of imaging spectrometer on target detection and recognition in real-time.