77 resultados para NPB (NAS parallel benchmarks)

em Chinese Academy of Sciences Institutional Repositories Grid Portal


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传统集群网络(cluster area network,简称cLAN)的评测模型主要考虑了延迟、带宽、路由、拥塞、网络拓扑结构等因素.但这些因素是否足以描述实际应用程序在集群上的通信行为,或者对其在集群系统上的性能给出一个很好的预测呢?当对NAS Parallel Benchmark(2.4版本)在集群系统深腾1800(DeepComp 1800)上进行大量测试时发现,集群网络的通信性能可以被一种特殊的通信模式(LU模式)所严重影响.更深入的研究表明,这个影响LU模式的因素是独立于前面所述的如延迟、带宽、路由、拥塞、网络拓扑结构等因素的.因此有必要对集群网络的评测模型重新进行审视,并增加一个新的性能评测因子以反映这个新发现的现象.从研究结果来看,这个重新审视也将对集群系统上的并行算法设计以及实际大规模科学计算的应用程序性能的优化提供一些新的思路.

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对3个国产万亿次机群系统进行了NPB性能测试分析,重点研究大规模并行处理时(处理器数目达到上千个)的性能特点和趋势.分析了不同的处理器、互连网络等系统配置对NPB性能的影响,发现NPB的8个程序在3个万亿次机器上的性能特点和表现并不一致,表明国产高性能机群在设计上正在逐渐走出同质化的趋势,向多样化发展.进一步分析表明,目前NPB程序的可扩展性可以达到几百个处理器,但尚不能达到上千个处理器,NPB程序能发挥出的系统峰值的百分比仍然徘徊在10%左右,机群系统的并行可扩展性和应用程序对机器运算潜能的利用还需要进一步提高.对于处理器数目达到上千个的万亿次机群系统来说,对集合通信和细粒度通信能力的支持亟需提高.

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解决平行平板流槽每次实验只能观测壁面培养细胞受一种剪应力作用的问题。作者在平行平板流槽的基础上,首次提出了一种改进后的流槽--二维平板分叉流槽。通过数值模拟,给出了流体作定常流动时,流速和壁面剪应力的分布。结果发现,利用这种二维平板分叉流槽可以研究壁面培养的细胞在不同大小剪应力作用下的力学行为。该研究结果为流槽的合理设计和使用,并分析剪应力空间分布对内皮细胞的影响有重要实际意义。

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A label-free protein microfluidic array for immunoassays based on the combination of imaging ellipsometry and an integrated microfluidic system is presented. Proteins can be patterned homogeneously on substrate in array format by the microfluidic system simultaneously. After preparation, the protein array can be packed in the microfluidic system which is full of buffer so that proteins are not exposed to denaturing conditions. With simple microfluidic channel junction, the protein microfluidic array can be used in serial or parallel format to analyze single or multiple samples simultaneously. Imaging ellipsometry is used for the protein array reading with a label-free format. The biological and medical applications of the label-free protein microfluidic array are demonstrated by screening for antibody–antigen interactions, measuring the concentration of the protein solution and detecting five markers of hepatitis B.

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An experimental investigation was conducted to study the holdup distribution of oil and water two-phase flow in two parallel tubes with unequal tube diameter. Tests were performed using white oil (of viscosity 52 mPa s and density 860 kg/m(3)) and tap water as liquid phases at room temperature and atmospheric outlet pressure. Measurements were taken of water flow rates from 0.5 to 12.5 m(3)/h and input oil volume fractions from 3 to 94 %. Results showed that there were different flow pattern maps between the run and bypass tubes when oil-water two-phase flow is found in the parallel tubes. At low input fluid flow rates, a large deviation could be found on the average oil holdup between the bypass and the run tubes. However, with increased input oil fraction at constant water flow rate, the holdup at the bypass tube became close to that at the run tube. Furthermore, experimental data showed that there was no significant variation in flow pattern and holdup between the run and main tubes. In order to calculate the holdup in the form of segregated flow, the drift flux model has been used here.

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<正>生物力学研究的趋势十分明显的是,由宏观方面的研究转向细观和微观方面的研究。人们从个体、器官和组织的生物力学方面,转向细胞甚至分子水平的研究。在力的作用下,细胞的形态、生理作用等发生的变化引起了人们极大的兴趣,其中流体流动时剪应力对细胞的作用尤为人们所特别关注,因为有血液在血管中流动时的剪应力对血管内皮细胞的作用这样的实际生理背景。剪应力不但可以影响内皮细胞的形态结构,而且对在细胞诸多生理方面有影响。

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A three-dimensional MHD solver is described in the paper. The solver simulates reacting flows with nonequilibrium between translational-rotational, vibrational and electron translational modes. The conservation equations are discretized with implicit time marching and the second-order modified Steger-Warming scheme, and the resulted linear system is solved iteratively with Newton-Krylov-Schwarz method that is implemented by PETSc package. The results of convergence tests are plotted, which show good scalability and convergence around twice faster when compared with the DPLR method. Then five test runs are conducted simulating the experiments done at the NASA Ames MHD channel, and the calculated pressures, temperatures, electrical conductivity, back EMF, load factors and flow accelerations are shown to agree with the experimental data. Our computation shows that the electrical conductivity distribution is not uniform in the powered section of the MHD channel, and that it is important to include Joule heating in order to calculate the correct conductivity and the MHD acceleration.

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It has long been recognized that many direct parallel tridiagonal solvers are only efficient for solving a single tridiagonal equation of large sizes, and they become inefficient when naively used in a three-dimensional ADI solver. In order to improve the parallel efficiency of an ADI solver using a direct parallel solver, we implement the single parallel partition (SPP) algorithm in conjunction with message vectorization, which aggregates several communication messages into one to reduce the communication costs. The measured performances show that the longest allowable message vector length (MVL) is not necessarily the best choice. To understand this observation and optimize the performance, we propose an improved model that takes the cache effect into consideration. The optimal MVL for achieving the best performance is shown to depend on number of processors and grid sizes. Similar dependence of the optimal MVL is also found for the popular block pipelined method.

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A direct twos-complement parallel array multiplication algorithm is introduced and modified for digital optical numerical computation. The modified version overcomes the problems encountered in the conventional optical twos-complement algorithm. In the array, all the summands are generated in parallel, and the relevant summands having the same weights are added simultaneously without carries, resulting in the product expressed in a mixed twos-complement system. In a two-stage array, complex multiplication is possible with using four real subarrays. Furthermore, with a three-stage array architecture, complex matrix operation is straightforwardly accomplished. In the experiment, parallel two-stage array complex multiplication with liquid-crystal panels is demonstrated.

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On the basis of signed-digit negabinary representation, parallel two-step addition and one-step subtraction can be performed for arbitrary-length negabinary operands.; The arithmetic is realized by signed logic operations and optically implemented by spatial encoding and decoding techniques. The proposed algorithm and optical system are simple, reliable, and practicable, and they have the property of parallel processing of two-dimensional data. This leads to an efficient design for the optical arithmetic and logic unit. (C) 1997 Optical Society of America.

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A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (C) 1999 Optical Society of America.

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Based on birefringence, a building-block stacking technique is suggested in this paper. A solid-state optical morphological processor module is thus developed, which is an integration of a beam array generator submodule, an optical connector submodule, and a Pockels readout optical modulator. It is shown that the technique is compact in construction, simple for fabrication, and insensitive to the environment.

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Negabinary is a component of the positional number system. A complete set of negabinary arithmetic operations are presented, including the basic addition/subtraction logic, the two-step carry-free addition/subtraction algorithm based on negabinary signed-digit (NSD) representation, parallel multiplication, and the fast conversion from NSD to the normal negabinary in the carry-look-ahead mode. All the arithmetic operations can be performed with binary logic. By programming the binary reference bits, addition and subtraction can be realized in parallel with the same binary logic functions. This offers a technique to perform space-variant arithmetic-logic functions with space-invariant instructions. Multiplication can be performed in the tree structure and it is simpler than the modified signed-digit (MSD) counterpart. The parallelism of the algorithms is very suitable for optical implementation. Correspondingly, a general-purpose optical logic system using an electron trapping device is suggested. Various complex logic functions can be performed by programming the illumination of the data arrays without additional temporal latency of the intermediate results. The system can be compact. These properties make the proposed negabinary arithmetic-logic system a strong candidate for future applications in digital optical computing with the development of smart pixel arrays. (C) 1999 Society of Photo-Optical Instrumentation Engineers. [S0091-3286(99)00803-X].