Impact of polarized illumination on high NA imaging in ArF immersion lithography at 45 nm node

Immersion lithography has been considered as the mainstream technology to extend the feasibility of optical lithography to further technology nodes. Using proper polarized illumination in an immersion lithographic tool is a powerful means to enhance the image quality and process capability for high numerical aperture (NA) imaging. In this paper, the impact of polarized illumination on high NA imaging in ArF immersion lithography for 45 nm dense lines and semi-dense lines is studied by PROLITH simulation. The normalized image log slope (NILS) and exposure defocus (ED) window are simulated under various polarized illumination modes, and the impact of polarized illumination on image quality and process latitude is analyzed. (C) 2007 Elsevier GmbH. All rights reserved.

A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.