A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

MODIFIED DIRECT TWOS-COMPLEMENT PARALLEL ARRAY MULTIPLICATION ALGORITHM FOR COMPLEX MATRIX OPERATION

A direct twos-complement parallel array multiplication algorithm is introduced and modified for digital optical numerical computation. The modified version overcomes the problems encountered in the conventional optical twos-complement algorithm. In the array, all the summands are generated in parallel, and the relevant summands having the same weights are added simultaneously without carries, resulting in the product expressed in a mixed twos-complement system. In a two-stage array, complex multiplication is possible with using four real subarrays. Furthermore, with a three-stage array architecture, complex matrix operation is straightforwardly accomplished. In the experiment, parallel two-stage array complex multiplication with liquid-crystal panels is demonstrated.

Direct detection of Yersinia pestis from the infected animal specimens by a fiber optic biosensor

The FOB-3, anew type fiber optic biosensor, is designed to rapidly detect a variety of biological agents or analytes with better stability, sensitivity and specificity. In order to detect Y. Pestis, a sandwich immunoassay was developed by using the purified antibody against antigen FI immobilized on polystyrene probes as the capture antibody and the monoclonal antibody-Cy5 conjugate as the detector. After a series of optimization for the stability, sensitivity and specificity of the FOB-3, 50-1000 ng/ml of antigen FI and 6 x 10(1)-6 x 10(7) CFU/ml Y. pestis could be detected constantly in about 20 min, and Y pestis could be detected specifically from Y. pseudotuberculosis, Y. enterocolitica, B. anthracis and E. coli. Then, 39 blind samples, including 27 tissues of mice infected with Y pestis and 12 tissues of healthy mice as negative control, were detected with the FOB-3. 92.6% infected tissues were identified from the tissues of healthy mice and the tissues containing more than 100 CFU/ml bacteria could be detected by the biosensor. The results demonstrated the feasibility of the FOB-3 as an effective method to detect Y. pestis rapidly and directly from the infected animal specimens with the advantage of portability, simple-operation as well as high sensitivity and specificity. (c) 2006 Elsevier B.V. All rights reserved.

A New Method to Investigate InGaAsP Single-Photon Avalanche Diodes Using a Digital Sampling Oscilloscope

A near-infrared single-photon detection system is established by using pigtailed InGaAs/InP avalanche photodiodes. With a 50GHz digital sampling oscilloscope, the function and process of gated-mode (Geiger-mode) single-photon detection are intuitionally demonstrated for the first time. The performance of the detector as a gated-mode single-photon counter at wavelengths of 1310 and 1550nm is investigated. At the operation temperature of 203K,a quantum efficiency of 52% with a dark count probability per gate of 2. 4 * 10~(-3), and a gate pulse repetition rate of 50kHz are obtained at 1550nm. The corresponding parameters are 43% , 8. 5 * 10~(-3), and 200kHz at 238K.

Fast simulation of the forward tracking detector of HPLUS

The necessity of installing a forward tracking detector stack is discussed for the Hadron Physics LanzhoU Spectrometer(HPLUS). A local tracker is developed to solve the multi-track finding problem. The track candidates are searched iteratively via Hough Transform. The fake tracks are removed by a least square fitting process. With this tracker we have studied the feasibility of pp -> pp + phi(-> K+K-), a typical physical channel proposed on HPLUS. The single track momentum resolution due to the uncertainty of the positioning in FTD is 1.3%. The multiple scattering effect contributes about 20% to the momentum resolution in the FTD coverage. The width and the signal-to-background ratio of the reconstructed phi are 1.51 MeV and 4.36, respectively, taking into account the direct Kaon channel pp -> pp + K+K- as background. The geometry coverage of FTD for phi events is about 85.4%. Based on the current fast simulation and estimation, the geometrical configuration of FTD meets the physical requirement of HPLUS under the current luminosity and multiplicity conditions. The tracker is applicable in the full simulation coming next and is extendable to other tracking component of HPLUS.

Parton energy loss in heavy-ion collisions via direct-photon and charged-particle azimuthal correlations

Charged-particle spectra associated with direct photon (gamma(dir)) and pi(0) are measured in p + p and Au + Au collisions at center-of-mass energy root(S)(NN) = 200 GeV with the STAR detector at the Relativistic Heavy Ion Collider. A shower-shape analysis is used to partially discriminate between gamma(dir) and pi(0). Assuming no associated charged particles in the gamma(dir) direction ( near side) and small contribution from fragmentation photons (gamma(frag)), the associated charged-particle yields opposite to gamma(dir) (away side) are extracted. In central Au + Au collisions, the charged-particle yields at midrapidity (vertical bar eta vertical bar < 1) and high transverse momentum (3 < (assoc)(PT) < 16 GeV/c) associated with gamma(dir) and pi(0) (vertical bar eta vertical bar < 0.9, 8 < (trig)(PT) < 16 GeV/c) are suppressed by a factor of 3-5 compared with p + p collisions. The observed suppression of the associated charged particles is similar for gamma(dir) and pi(0) and independent of the gamma(dir) energy within uncertainties. These measurements indicate that, in the kinematic range covered and within our current experimental uncertainties, the parton energy loss shows no sensitivity to the parton initial energy, path length, or color charge.

Direct electrochemical detection of glucose in human plasma on capillary electrophoresis microchips

We developed an electrochemical detector on a hybrid chip for the determination of glucose in human plasma. The microchip system described in this paper consists of a poly(dimethylsiloxane) (PDMS) layer containing separation and injection channels and an electrode plate. The copper microelectrode is fabricated by selective electroless deposition. The fabrication of the decoupler is performed by platinum electrochemical deposition on the metal film formed by electroless deposition. Factors influencing the performance, including detection potential, separation field strength, and buffer concentration, were studied. The electrodes exhibited good stability and durability in the analytical procedures. Under optimized detection conditions, glucose responded linearly from 10 muM to 1 mM. Finally, glucose in human plasma from three healthy individuals and two diabetics was successfully determined, giving a good prospect for a new clinical diagnostic instrument.

DIRECT-INJECTION OF URINE AND DETERMINATION OF ACETAMINOPHEN BY MICELLAR LIQUID-CHROMATOGRAPHY WITH A WALL-JET CELL CARBON-FIBER MICROELECTRODE

A wall-jet cell/carbon fibre microelectrode detector was designed and used for the micellar liquid chromatographic assay of acetaminophen. The separations were carried out in an analytical column packed with C-18 stationary phase and the mobile phase was