10 resultados para Digital design

em Chinese Academy of Sciences Institutional Repositories Grid Portal


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智能制造装备的设计水平不高是制约我国装备制造业发展因素之一。在阐述智能制造装备特点的基础上,提出了一种基于CORBA规范的智能制造装备数字化设计与验证系统的体系结构,并探讨了实现该系统的关键技术。该系统的目的是降低智能制造设备开发成本,缩短开发周期,提高智能制造装备的设计质量。

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该文提出将虚拟样机技术应用于工业机器人仿真研究过程 ,研究与开发工业机器人虚拟样机系统。首先说明虚拟样机技术并分析其关键技术 ,然后说明了工业机器人虚拟样机系统的构成与样机系统在机器人仿真研究中的研究内容。总结该项技术主要解决以下两方面的问题 ,即机器人仿真研究中的系统集成及为以机器人为主体的生产线虚拟设计、验证环境提供底层的数字化环境

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设计了一种应用于兰州重离子加速器注入器的电源控制器,该控制器基于微处理器AT-mega128,结合MAX7000系列的复杂可编程器件和RTL8019AS网关芯片来实现对电源系统的控制,并通过RS-232总线实现与上位机的串口通信。应用结果表明,该控制器具有良好的通用性、灵活性、可远程控制及性能稳定等特点,实现了注入器磁铁电源10-4量级的幅度稳定性,使注入器引出的束流强度、束流品质、束流稳定性和供束效率等得到很大的提高。

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介绍了一种基于CPLD设计的电源控制模块,并且利用Atmegal128单片机和RTL8019S实现逻辑功能和远程控制功能。该电源系统主要用于重离子加速器注入器(SFC)中,具有很好的灵活性、可远程控制、性能稳定等特点。

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In petawatt laser system, the gratings used to compose pulse compressor are very large in size which can be only acquired currently by arraying small aperture gratings to form a large one instead, an approach referred to as grating tiling. Theory and experiments have demonstrated that the coherent addition of multiple small gratings to form a larger grating is viable, the key technology of which is to control the relative position and orientation of each grating with high precision. According to the main factors that affect the performance of the grating tiling, a 5-DOF ultraprecision stage is developed for the grating tiling experiment. The mechanism is formed by serial structures. The motion of the mechanism is guided by flexure hinges and driven by piezoelectric actuators and the movement resolution of which can achieve nanometer level. To keep the stability of the mechanism, capacitive position sensors with nanometer accuracy are fixed on it to provide feedback signals with which to realize closed-loop control, thus the positioning precision of the mechanism is within several nanometers range through voltage control and digital PID algorithm. Results of experiments indicate that the performance of the mechanism can meet the requirement of precision for grating tiling.}

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This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

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This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

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A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

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This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

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We designed and fabricated GaAs OMIST (Optical-controlled Metal-Insulator-Semiconductor Thyristor) device. Using oxidation of A1As layer that is grown by MBE form the Ultra-Thin semi-Insulating layer (UTI) of the GAAS OMIST. The accurate control and formation of high quality semi-insulating layer (AlxOy) are the key processes for fabricating GaAs OMIST. The device exhibits a current-controlled negative resistance region in its I-V characteristics. When illuminated, the major effect of optical excitation is the reduction of the switching voltage. If the GaAs OMIST device is biased at a voltage below its dark switching voltage V-s, sufficient incident light can switch OMIST from high impedance low current"off"state to low impedance high current "on"state. The absorbing material of OMIST is GaAs, so if the wavelength of incident light within 600 similar to 850nm can be detected effectively. It is suitable to be used as photodetector for digital optical data process. The other attractive features of GaAs OMIST device include suitable conducted current, switching voltage and power levels for OEIC, high switch speed and high sensitivity to light or current injection.