基于场景的笔式界面设计工具的设计和实现

设计实现了一个基于数字笔的用户界面设计工具，该工具以面向笔式界面领域，基于场景的设计思想来设计系统中的界面场景组织关系以及场景之间的动态切换方式，设计者与工具间的交互自然流畅、快捷高效。通过手势识别技术，该工具可以将场景的设计结果转换为内部的界面描述语言，并通过相应的解释最终构造生成笔式用户界面。该工具可以快速生成界面原型，从而有效地提高了笔式交互系统的设计和开发效率。

基于场景方法的笔式界面软件设计工具

为缩短的笔式用户界面软件的开发周期,让设计人员对软件的整体构思在开发过程中得以保持,提高团队人员的交流效率,提出了有关笔式界面软件的文档描述规范PUIML(pen-based user interface modeling language),并设计实现了一个笔交互的笔式用户界面软件设计工具。以笔式操作平台为软件平台,以PUIML为数据模型,采用基于场景设计的开发方法,为设计人员和用户提供自然的纸笔交互方式,设计结果形成PUIML形式的文档,通过主控程序执行。实践结果表明,使用PUI Maker可以解决笔式用户界面开发中存在的以开发人员为中心,原始设计与开发结果不一致等问题,提高了笔式界面软件的开发效率。

The design and verification of FPGA CAD toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

A Synthesis Tool for a Tile-Based Heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.