Design and simulation of charge sensitive preamplifier with CMOS FET implemented as feedback capacitor C-fp

In this paper, to design a new preamplifier for optimum performances with charged-particle or heavy-ion detectors, the CMOS FET is implemented as a feedback capacitor C-fp, so that the entire system should be built only with MOSFET. This work is a revolution design because to realize an ASIC for a preamplifier circuit, the capacitor will also be included. We succeed after a simulation to maintain a rise time less than 3 ns, the output resistance less than 94 Omega and the linearity almost good.

A low noise charge sensitive preamplifier with switch control feedback resistance

In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94 Omega and the linearity almost good.

An ultra-low power CMOS random number generator

This paper proposes an ultra-low power CMOS random number generator (RING), which is based on an oscillator-sampling architecture. The noisy oscillator consists of a dual-drain MOS transistor, a noise generator and a voltage control oscillator. The dual-drain MOS transistor can bring extra-noise to the drain current or the output voltage so that the jitter of the oscillator is much larger than the normal oscillator. The frequency division ratio of the high-frequency sampling oscillator and the noisy oscillator is small. The RNG has been fabricated in a 0.35 mu m CMOS process. It can produce good quality bit streams without any post-processing. The bit rate of this RNG could be as high as 100 kbps. It has a typical ultra-low power dissipation of 0.91 mu W. This novel circuit is a promising unit for low power system and communication applications. (c) 2007 Elsevier Ltd. All rights reserved.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A bistable, self-latching inverter by the monolithic integration of resonant tunnelling diode and high electron mobility transistor

This paper reports that the structures of AlGaAs/InGaAs high electron mobility transistor (HEMT) and AlAs/GaAs resonant tunnelling diode (RTD) are epitaxially grown by molecular beam epitaxy ( MBE) in turn on a GaAs substrate. An Al0.24Ga0.76As chair barrier layer, which is grown adjacent to the top AlAs barrier, helps to reduce the valley current of RTD. The peak-to-valley current ratio of fabricated RTD is 4.8 and the transconductance for the 1-mu m gate HEMT is 125mS/mm. A static inverter which consists of two RTDs and a HEMT is designed and fabricated. Unlike a conventional CMOS inverter, the novel inverter exhibits self-latching property.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

CMOS工艺的优化设计与分析

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

CMOS工艺的优化设计与分析（详细摘要）

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

低温高速CMOS电路的特性分析和设计制造

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

薄场铝栅CMOS技术-器件电参数分析及大生产的工艺控制

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

DYL和CMOS电路兼容集成研究

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

CMOS门阵列设计工具

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

低温高速CMOS电路的特性分析和设计制造

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

低温高速CMOS电路的特性分析和设计制造

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z