Design consideration and performance of high-power and high-brightness InGaAs-InGaAsP-AlGaAs quantum-well diode lasers (lambda=0.98 mu m)

In this paper, we conduct a theoretical analysis of the design, fabrication, and performance measurement of high-power and high-brightness strained quantum-well lasers emitting at 0.98 mum, The material system of interest consists of an Al-free InGaAs-InGaAsP active region and AlGaAs cladding layers. Some key parameters of the laser structure are theoretically analyzed, and their effects on the laser performance are discussed. The laser material is grown by metal-organic chemical vapor deposition and demonstrates high quality with low-threshold current density, high internal quantum efficiency, and extremely low internal loss. High-performance broad-area multimode and ridge-waveguide single-mode laser devices are fabricated. For 100-mum-wide stripe lasers having a cavity length of 800 mum, a high slope efficiency of 1.08 W-A, a low vertical beam divergence of 34 degrees, a high output power of over 4.45 W, and a very high characteristic temperature coefficient of 250 K were achieved. Lifetime tests performed at 1.2-1.3 W (12-13 mW/mum) demonstrates reliable performance. For 4-mum-wide ridge waveguide single-mode laser devices, a maximum output power of 394 mW and fundamental mode power up to 200 mW with slope efficiency of 0.91 mW/mum are obtained.

High power 980 nm Al-free strained quantum-well lasers for erbium-doped fiber amplifiers

In this paper, we reported on the fabrication of 980 nm InGaAs/InGaAsP strained quantum-well (QW) lasers with broad waveguide. The laser structure was grown by low-pressure metalorganic chemical vapor deposition on a n(+)- GaAs substrate. For 3 mu m stripe ridge waveguide lasers, the threshold current is 30 mA and the maximum output power and the output power operating in fundamental mode are 350 mW and 200 mW, respectively. The output power from the single mode fiber is up to 100 mW, the coupling efficiency is 50%. We also fabricated 100 mu m broad stripe coated lasers with cavity length of 800 mu m, a threshold current density of 170 A/cm(2), a high slope efficiency of 1.03 W/A and a far-field pattern of 40 x 6 degrees are obtained. The maximum output power of 3.5 W is also obtained for 100 mu m wide coated lasers. (C) 2000 Elsevier Science B.V. All rights reserved.

Performing Fast Addition and Multiplication by Transferring Single Electrons

This paper proposes novel fast addition and multiplication circuits that are based on non-binary redundant number systems and single electron (SE) devices. The circuits consist of MOSFET-based single-electron (SE) turnstiles. We use the number of electrons to represent discrete multiple-valued logic states and we finish arithmetic operations by controlling the number of electrons transferred. We construct a compact PD2,3 adder and a 12x12bit multiplier using the PD2,3 adder. The speed of the adder can be as high as 600MHz with 400nW power dissipation. The speed of the adder is regardless of its operand length. The proposed circuits have much smaller transistors than conventional circuits.

Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

Simulation of single electronic device and robust circuit construction

The article mainly focuses on the simulation of the single electron device and circuit. The orthodox model of single electronic device is introduced and the simulation with Matlab and Pspice is illustrated in the article. Moreover, the built of robust circuit using single electronic according to neural network is done and the simulation is also included in the paper. The result shows that neural network added with proper redundancy is an available candidate for single electron device circuit. The proposed structure is also promising for the realization of low ultra-low power consumption and solution of transient device failure.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

A direct-conversion mixer with a DC-offset cancellation for WLAN

This paper presents a 5GHz double-balanced mixer with DC-offset cancellation circuit for direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard. The analog feedback loop is used, to eliminate the DC-offset at the output of the double-balanced mixer. The test results show that the mixer with DC-offset cancellation circuit has voltage conversion gain of 9.5dB at 5.15GHz, noise figure of 13.5dB, IIP3 of 7.6 dBm, 1.73mV DC-offset voltage and 67mW power with 3.3-V power supply. The DC-offset cancellation circuit has less than 0.1mm(2) additional area and 0.3mW added power dissipation. The direct conversion WLAN receiver has been implemented in a 0.35 mu m SiGe BiCMOS technology.

A Low Power Baseband Chain for CMMB Application

This paper presents experimental results of an analog baseband circuit for China Multimedia Mobile Broadcasting (CMMB) direct conversion receiver in 0.35um SiGe BiCMOS process. It is the first baseband of CMMB RFIC reported so far. A 8(th)-order chebyshev low pass filter (LPF) with calibration system is used in the analog baseband circuit, the filter provides 0.5 dB passband ripple and -35 dB attenuation at 6MHz with the cutoff frequency at 4MHz, the calibration of filter is reported to achieve the bandwidth accuracy of 3%. The baseband variable gain amplifier (VGA) achieves more than 40 dB gain tuning with temperature compensation. In addition, A DC offset cancellation circuit is also introduced to remove the offset from layout and self-mixing, and the remaining offset voltage and current consumption are only 6mV and 412uA respectively. Implemented in a 0.35um SiGe technology with 1.1 mm(2) die size, this tuner baseband achieves OIP3 of 25.5 dBm and dissipate 16.4 mA under 2.8-V supply.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

A 5GHz low power WLAN transceiver SiGe RFIC for personal communication terminal applications

A low-cost low-power single chip WLAN 802.11a transceiver is designed for personal communication terminal and local multimedia data transmission. It has less than 130mA current dissipation, maximal 67dB gain and can be programmed to be 20dB minimal gain. The receiver system noise figure is 6.4dB in hige-gain mode.

High efficiency RFID UHF power converter

The paper proposes a high efficiency RFID UHF power converter unit to overcome the low efficiency problem. This power converter is mainly composed of an RF-DC converter and a DC-DC converter. In order to overcome the low efficiency problem in low current consuming condition, a DC-DC converter is added to conventional single RF-DC converter rectifier to increase the rectifying efficiency of the RFDC rectifier. The power converter is implemented in a 0.18 um mixed signal, 1p6m CMOS technology. Simulation shows the power converter has an average improvement of 5% and can achieve efficiency as high as 30% with 900MHz, 16uW RF input power and 1.3 V 3.6uA DC output.

A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

Single-mode holey vertical-cavity surface-emitting laser with ultra-narrow beam divergence

We demonstrated oxide-confined 850-nm vertical-cavity surface-emitting lasers (VCSELs) with a two-dimensional petal-shaped holey structure composed of several annular-sector-shaped holes. Four types of devices with different hole numbers were designed and fabricated. The measured results showed that the larger hole number was beneficial to purifying the lasing mode, and realizing the single-mode operation. The side mode suppression ratio (SMSR) exceeded 30 dB throughout the entire drive current. Mode selective loss mechanism was used to explain the single-mode characteristic. The single-mode devices possessed good beam profiles, and the lowest divergence angle was as narrow as 3.2 degrees (full width at half maximum), attributed to the graded index profile and the shallow etching in the top distributed Bragg reflector (DBR).

12 W high efficiency single frequency ring laser

Single-frequency output power of 12 W at 1064 nm is demonstrated. Pumped by a fiber-coupled diode laser, the Nd:YVO4 produces 58.6% of the slope efficiency with respect to absorbed pump power, and 52.7% of the optical-optical efficiency and nearly diffraction-limited output with a beam quality parameter of M-2 approximate to 1.11. To the best of our knowledge, this is the highest slope efficiency and optical-optical efficiency in single-frequency Nd:YVO4 ring laser. The slope efficiency of the single frequency laser is close to the limit of the efficiency. [GRAPHICS] output spectrum of the single-frequency Nd:YVO4 ring laser

Dynamics of Multi-Stage Bladed Disks Systems

This paper presents a new and original method for dynamical analysis of multistage cyclic structures such as turbomachinery compressors or turbines. Each stage is modeled cyclically by its elementary sector and the interstage coupling is achieved through a cyclic recombination of the interface degrees of freedom. This method is quite simple to set up; it allows us to handle the finite element models of each stage's sector directly and, as in classical cyclic symmetry analysis, to study the nodal diameter problems separately. The method is first validated on a simple case study which shows good agreements with a complete 360 deg reference calculation. An industrial example involving two HP compressor stages is then presented. Then the forced response application is presented in which synchronous engine order type excitations are considered.