A proposal for low cross-talk square-lattice photonic crystal waveguide intersection utilizing the symmetry of waveguide modes

We propose an approach to construct waveguide intersections with broad bandwidth and low cross-talk for square-lattice photonic crystals. by utilizing a vanishing overlap of the propagation modes in the waveguides created by defects which support dipole-like defect modes. The finite-difference time-domain method is used to simulate the waveguide intersection created in the two-dimensional square-lattice photonic crystals. Over a bandwidth of 30 nm with the center wavelength at 1300 nm, transmission efficiency above 90% is obtained with cross-talk below -30 dB. Especially, we demonstrate the transmission of a 500-fs pulse at 1.3 Am through the intersection, and the pulse after transmission shows very little distortion while the cross-talk remains at low level meantime. (c) 2006 Elsevier B.V. All rights reserved.

Geometry parameter optimization of large cross-sectional S-shaped bent rib waveguides for silicon based optical switches

地址: Chinese Acad Sci, Inst Semicond, State Key Lab Integrated Optoelect, Beijing 100083, Peoples R China

Fabrication of 4 x 4 tapered MMI coupler with large cross section

MMI coupler with large cross section has low coupling loss between the device and fiber. However, large chip area is required. Recently proposed N x N tapered MMI coupler shows a substantial reduction in device geometry. No such kind of devices with N > 2 has yet been realized up to now. The authors have demonstrated a 4 x 4 parabolically tapered MMI coupler with large cross section that can match the SM fiber in silicon-on-insulator (SOI) technology. The device exhibits a minimum uniformity of 0.36 dB and excess loss of 3.7 dB, It represents a key component for realization of MMI-based silicon integrated optical circuit technology.

A Synthesis Tool for a Tile-Based Heterogeneous FPGA

A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental results based MCNC benchmarks to show that the integration of the synthesis tool and the FPGA architecture can achieve high performance in the targeted FPGA applications. In addition, Vsyn can also target embedded special-purpose macros for the heterogeneous FPGA.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.