Lossless data compression scheme based on neural network and SVM

First, the compression-awaited data are regarded Lis character strings which are produced by virtual information source mapping M. then the model of the virtual information source M is established by neural network and SVM. Last we construct a lossless data compression (coding) scheme based oil neural network and SVM with the model, an integer function and a SVM discriminant. The scheme differs from the old entropy coding (compressions) inwardly, and it can compress some data compressed by the old entropy coding.

Interdot interaction induced zero-bias maximum of the differential conductance in parallel double quantum dots

We have studied the equilibrium and nonequilibrium electronic transports through a double quantum dot coupled to leads in a symmetrical parallel configuration in the presence of both the inter- and the intradot Coulomb interactions. The influences of the interdot interaction and the difference between dot levels on the local density of states (LDOS) and the differential conductance are paid special attention. We find an interesting zero-bias maximum of the differential conductance induced by the interdot interaction, which can be interpreted in terms of the LDOS of the two dots. Due to the presence of the interdot interaction, the LDOS peaks around the dot levels epsilon(i) are split, and as a result, the most active energy level which supports the transport is shifted near to the Fermi level of the leads in the equilibrium situation. (c) 2006 American Institute of Physics.

New finite-difference scheme for simulations of step-index waveguides with tilt interfaces

A new finite-difference scheme is presented for the second derivative of a semivectorial field in a step-index optical waveguide with tilt interfaces. The present scheme provides an accurate description of the tilt interface of the nonrectangular structure. Comparison with previously presented formulas shows the effectiveness of the present scheme.

Negative differential resistance and the transition to current self-oscillation in GaAs/AlAs superlattices

We investigate the transition from static to dynamic electric field domains (EFDs) in a doped GaAs/AlAs superlattice (SL). We show that a transverse magnetic field and/or the temperature can induce current self-oscillations. This observation can be attributed to the negative differential resistance (NDR) effect. Transverse magnetic field and the temperature can increase the NDR of a doped SL. A large NDR can lead to an unstable EFD in a certain range of d.c. bias. (C) 1999 Elsevier Science Ltd. All rights reserved.

Interference effects in differential reflectance spectra of the GaAs epilayers grown on Si substrate

We report the observation of oscillating features in differential reflectance spectra from the GaAs epilayer grown on Si substrate in the energy range both below and above the fundamental band gap. It is demonstrated that the oscillating features are due to the difference in the interference between two neighboring areas of the sample. The interference arises from two light beams reflected from different interfaces of the sample. The calculated spectra in the nonabsorption region are in good agreement with measured data. It is shown that the interference effect can be used as a sensitive method to characterize the inhomogeneity of the semiconductor heterostructures. (C) 1998 American Institute of Physics. [S0021-8979(98)08723-4].

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

A two-step backoff scheme for improving the performance of the IEEE 802.11 distributed coordination function

This paper describes the binary exponential backoff mechanism of 802.11 distributed coordination function (DCF), and introduces some methods of modifying the backoff scheme. Then a novel backoff scheme, called Two-step Backoff scheme, is presented and illustrated. The simulation process in OPNET environment has been described also. At last, the analysis and simulation results show that the Two-step backoff scheme can enhance the performance of the IEEE 802.11 DCF.

A power-saving scheme for IEEE 802.11 Ad hoc networks

In the Wireless Local Area Networks (WLANs), the terminals are often powered by battery, so the power-saving performance of the wireless network card is a very important issue. For IEEE 802.11 Ad hoc networks, a power-saving scheme is presented in Medium Access Control (MAC) layer to reduce the power consumption by allowing the nodes enter into the sleep mode, but the scheme is based on Time-Drive Scheme (TDS) whose power-saving efficiency becomes lower and lower with the network load increasing. This paper presented a novel energy-saving mechanism, called as Hybrid-Drive Scheme (HDS), which introduces into a Message.-Drive Scheme (MDS) and combines MDS with the conventional TDS. The MDS, could obtain high efficiency when the load is heavy; meanwhile the TDS has high efficiency when the network load is small. The analysis shows that the proposed HDS could obtain high energy-efficiency whether the network load is light or heavy and have higher energy-saving efficiency than conventional scheme in the IEEE 802.11 standard.

Proposed scheme for parallel 10Gb/s VSR system and its Verilog HDL realization

This paper proposes a novel and innovative scheme for 10Gb/s parallel Very Short Reach (VSR) optical communication system. The optimized scheme properly manages the SDH/SONET redundant bytes and adjusts the position of error detecting bytes and error correction bytes. Compared with the OIF-VSR4-01.0 proposal, the scheme has a coding process module. The SDH/SONET frames in transmission direction are disposed as follows: (1) The Framer-Serdes Interface (FSI) gets 16x622.08Mb/s STM-64 frame. (2) The STM-64 frame is byte-wise stripped across 12 channels, all channels are data channels. During this process, the parity bytes and CRC bytes are generated in the similar way as OIF-VSR4-01.0 and stored in the code process module. (3) The code process module will regularly convey the additional parity bytes and CRC bytes to all 12 data channels. (4) After the 8B/10B coding, the 12 channels is transmitted to the parallel VCSEL array. The receive process approximately in reverse order of transmission process. By applying this scheme to 10Gb/s VSR system, the frame size in VSR system is reduced from 15552x12 bytes to 14040x12 bytes, the system redundancy is reduced obviously.