A 10 Gb/s Directly-Modulated 1.3 mu m InAs/GaAs Quantum-Dot Laser

We demonstrate 10 Gb/s directly-modulated 1.3 mu m InAs quantum-dot (QD) lasers grown on GaAs substrates by molecular beam epitaxy. The active region of the QD lasers consists of five-stacked InAs QD layers. Ridge-waveguide lasers with a ridge width of 4 mu m and a cavity length of 600 mu m are fabricated with standard lithography and wet etching techniques. It is found that the lasers emit at 1293 nm with a very low threshold current of 5 mA at room temperature. Furthermore, clear eye-opening patterns under 10 Gb/s modulation rate at temperatures of up to 50 degrees C are achieved by the QD lasers. The results presented here have important implications for realizing low-cost, low-power-consumption, and high-speed light sources for next-generation communication systems.

Self-consistent analysis of AlSb/InAs high electron mobility transistor structures

The influences of channel layer width, spacer layer width, and delta-doping density on the electron density and its distribution in the AlSb/InAs high electron mobility transistors (HEMTs) have been studied based on the self-consistent calculation of the Schrodinger and Poisson equations with both the strain and nonparabolicity effects being taken into account. The results show that, having little influence on the total two dimensional electron gas (2DEG) concentration in the channel, the HEMT's channel layer width has some influence on the electron mobility, with a channel as narrow as 100-130 angstrom being more beneficial. For the AlSb/InAs HEMT with a Te delta-doped layer, the 2DEG concentration as high as 9.1 X 10(12) cm(-2) can be achieved in the channel by enhancing the delta-doping concentration without the occurrence of the parallel conduction. When utilizing a Si delta-doped InAs layer as the electron-supplying layer of the AlSb/InAs HEMT, the effect of the InAs donor layer thickness is studied on the 2DEG concentration. To obtain a higher 2DEG concentration in the channel, it is necessary to use an InAs donor layer as thin as 4 monolayer. To test the validity of our calculation, we have compared our theoretical results (2DEG concentration and its distribution in different sub-bands of the channel) with the experimental ones done by other groups and show that our theoretical calculation is consistent with the experimental results.

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

A Hybrid Random Number Generator Using Single Electron Tunneling Junctions and MOS Transistors

This paper proposes a novel single electron random number generator (RNG). The generator consists of multiple tunneling junctions (MTJ) and a hybrid single electron transistor (SET)/MOS output circuit. It is an oscillator-based RNG. MTJ is used to implement a high-frequency oscillator,which uses the inherent physical randomness in tunneling events of the MTJ to achieve large frequency drift. The hybrid SET and MOS output circuit is used to amplify and buffer the output signal of the MTJ oscillator. The RNG circuit generates high-quality random digital sequences with a simple structure. The operation speed of this circuit is as high as 1GHz. The circuit also has good driven capability and low power dissipation. This novel random number generator is a promising device for future cryptographic systems and communication applications.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

基于MSP430 单片机和DS18B20 的多分支多通道温度测量系统远程监控软件

This paper present that the system can acquire the remote temperature measurement data of 40 monitoring points,through the RS-232 serial port and the Intranet.System s hardware is consist of TI s MSP430F149 mixed-signal processor and UA7000A network module.Using digital temperature sensor DS18B20,the structure is simple and easy to expand,the sensors directly send out the temperature data.MSP430F149 has the advantage of ultra-low-power and high degree of integration.Using msp430F149,the multi-branch multi-p...中文文摘：文章论述了通过RS-232串口和Intranet网络,来实现对远端的40个温度测量点的监控。系统硬件由TI公司的MSP430F149混合信号处理器和UA7000A网络模块构成。传感器采用数字式温度传感器DS18B20,它将直接得到温度的数字量,结构简单,易于扩展。MSP430F149处理器具有超低功耗和高度集成等优点,利用它构建的多分支多通道温度测量系统功能强大,结构简单,可靠性高,抗干扰能力强。系统客户端软件采用Microsoft Visual C++6.0设计。本监控系统能够很好地完成对4个分支共40个温度测量点的远程实时监控。

基于TCP/ IP 协议的CSR离子泵电源远程监控软件系统设计

This paper discuss a Ion-pump Power Supply control system making use of RS232 series bus and Intranet.The system s hardware VAC800 is composed of MSP430F149 mixed-signal processors produced by TI and UA7000A network model.MSP430F149 has advantages of ultra-low-power and high-integration.The Ion-pump Power Supply control system has the characteristics of strong function,simple structure,high reliability,strong resistance of noise,no peripheral chip,etc.Visual studio 2005 is used to design the system s softwa...中文文摘：论述了通过RS-232总线和Intranet网络,来实现对远端的离子泵电源的监测与控制。系统硬件VAC800由TI公司的MSP430F149混合信号处理器和UA7000A网络模块构成。MSP430F149具有超低功耗和高集成度等优点,利用它构建的离子泵电源监控系统功能强大,结构简单,可靠性高,抗干扰能力强。系统软件采用visual studio 2005设计。本监控系统能够很好地完成对加速器离子泵电源监视与控制。

ECC密码算法的低功耗硬件实现研究

椭圆曲线密码算法作为高安全性的公钥密码;ECC算法的优化和软硬件实现是当前的研究热点;采用硬件实现椭圆曲线密码算法具有速度快、安全性高的特点,随着功耗分析、旁路攻击等新型分析方法的发展,密码算法硬件实现中的低功耗设计越来越重要;针对椭圆曲线密码算法的特点,主要对该算法芯片设计中的低功耗设计方法进行探讨。

Realization of negative differential resistance and switching devices based on copper phthalocyanine by the control of evaporation rate

We have observed, respectively, a negative differential resistance (NDR) and switching conduction in current-voltage (I-V) characteristics of organic diodes based on copper phthalocyanine (CuPc) film sandwiched between indium-tin-oxide (ITO) and aluminum (Al) by controlling the evaporation rate. The NDR effect is repeatable which can be well, controlled by sweep rate and start voltage, and the switching exhibits write-once-read-many-times (WORM) memory characteristics. The traps in the organic layer and interfacial dipole have been used to explain the NDR effect and switching conduction. This opens up potential applications for CuPc organic semiconductor in low power memory and logic circuits.

Negative differential resistance effect in organic devices based on an anthracene derivative

The authors observed a negative differential resistance (NDR) in organic devices consisting of 9,10-bis-(9,9-diphenyl-9H-fluoren-2-yl)-anthracene (DPFA) sandwiched between Ag and indium tin oxide electrodes. The large NDR shown in current-voltage characteristics is reproducible, resulting in that the organic devices can be electrically switched between a high conductance state (on state) and a low conductance state (off state). It can be found that the currents at both on to off states are space-charge limited and attributed to the electron traps at the Ag/DPFA interface. The large and reproducible NDR makes the devices of tremendous potential in low power memory and logic circuits.

工业无线网络WIA标准体系与关键技术

工业无线技术是一种本世纪初新兴的、面向设备间信息交互的无线网络技术,适合在恶劣的工业现场环境下使用,具有强抗扰、低功耗、实时通信等技术特征,是对现有无线技术在工业应用方向上的功能扩展和技术创新,并将最终转化为新的无线技术标准。本文介绍我国在工业无线技术方面的研究进展,重点介绍具有自主知识产权的工业无线网络核心技术以及相关国家标准体系的建设情况。

基于DSP的动态传感器网络实验平台的设计和开发

介绍了一种基于DSP2812的动态传感器网络实验平台的设计与开发.该实验平台的设计由配备各种低成本、低功耗的传感器和无线通信模块的可移动的传感器节点组成.在介绍动态传感器网络实验平台的各个组成部分之后,对系统进行了的基本实验测试,并给出了测试结果.*

一种低功耗微弱信号放大电路的优化设计与研究

针对远距离声源发射的水声信号微弱、水声接收设备电源能量有限的特点,提出一种功耗小、对无源元件误差灵敏度低、高增益放大的微弱水声信号通用放大电路。系统采用场效应管共源单调谐放大器为前置放大级,由四级级联低功耗运放构成带通滤波放大电路,省去传统的R、C低通网络,实现了对微弱水声信号的高增益放大和海洋背景噪声的归一化处理。通过计算电路网络传递函数极点证明了电路系统的稳定性。海上使用表明系统具有精度高、适应性强、电路稳定性好、功耗小等优点。