126 resultados para hierarchical memory


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We have fabricated a set of samples of zincblende Mn-rich Mn(Ga)As clusters embedded in GaAs matrices by annealing (Ga,Mn)As films with different nominal Mn content at 650 degrees C. For the samples with Mn content no more than 4.5%, the Curie temperature reaches nearly 360 K. However, when Mn content is higher than 5.4%, the samples exhibit a spin-glass-like behavior. We suggest that these different magnetic properties are caused by the competing result of dipolar and Ruderman-Kittel-Kasuya-Yosida interaction among clusters. The low-temperature spin dynamic behavior, especially the relaxation effect, shows the extreme creeping effect which is reflected by the time constant tau of similar to 10(11) s at 10 K. We explain this phenomenon by the hierarchical model based on the mean-field approach. We also explain the memory effect by the relationship between the correlation function and the susceptibility.

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This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

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The transmission of electrons through a hierarchical self-assembly of GaAs/AlxGa(1-)xAs quantum dots (QDs) is calculated using the coupled-channel recursion method. Our results reveal that the number of conductance peaks does not change when the barrier widths change, but the intensities decrease as the barrier widths increase. The conductance peaks will shift towards low Fermi energies as the transverse width of GaAs QD increases, as the thickness of GaAs quantum well increases, or as the height of GaAs QDs decreases. Our calculated results may be useful in the application of QDs to photoelectric devices. (c) 2005 American Institute of Physics.

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We analyse the operation of a semiconductor nanowire-based memory cell. Large changes in the nanowire conductance result when the magnetization of a periodic array of nanoscale magnetic gates, which comprise the other key component of the memory cell, is switched between distinct configurations by an external magnetic field. The resulting conductance change provides the basis for a robust memory effect, which can be implemented in a semiconductor structure compatible with conventional semiconductor integrated circuits.

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Quantum-confined Stark effects in GaAs/AlxGa1-xAs self-assembled quantum dots are investigated theoretically in the framework of effective-mass envelope function theory. The electron and hole energy levels and optical transition energies are calculated in the presence of an electric field in different directions. In our calculation, the effect of finite offset, valence-band mixing, the effects due to the different effective masses of electrons and holes in different regions, and the real quantum dot structures are all taken into account. The results show that the electron and hole energy levels and the optical transition energies can cause blueshifts when the electric field is applied along the opposite to the growth direction. Our calculated results are useful for the application of hierarchical self-assembly of GaAs/AlxGa1-xAs quantum dots to photoelectric devices. (c) 2005 American Institute of Physics.

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The electronic structures in the hierarchical self-assembly of GaAs/AlxGa1-xAs quantum dots are investigated theoretically in the framework of effective-mass envelope function theory. The electron and hole energy levels and optical transition energies are calculated. In our calculation, the effect of finite offset, valence-band mixing, the effects due to the different effective masses of electrons and holes in different regions, and the real quantum dot structures are all taken into account. The results show that (1) electronic energy levels decrease monotonically, and the energy difference between the energy levels increases as the GaAs quantum dot (QD) height increases; (2) strong state mixing is found between the different energy levels as the GaAs QD width changes; (3) the hole energy levels decrease more quickly than those of the electrons as the GaAs QD size increases; (4) in excited states, the hole energy levels are closer to each other than the electron ones; (5) the first heavy- and light-hole transition energies are very close. Our theoretical results agree well with the available experimental data. Our calculated results are useful for the application of the hierarchical self-assembly of GaAs/AlxGa1-xAs quantum dots to photoelectric devices.

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A hierarchical equations of motion formalism for a quantum dissipation system in a grand canonical bath ensemble surrounding is constructed on the basis of the calculus-on-path-integral algorithm, together with the parametrization of arbitrary non-Markovian bath that satisfies fluctuation-dissipation theorem. The influence functionals for both the fermion or boson bath interaction are found to be of the same path integral expression as the canonical bath, assuming they all satisfy the Gaussian statistics. However, the equation of motion formalism is different due to the fluctuation-dissipation theories that are distinct and used explicitly. The implications of the present work to quantum transport through molecular wires and electron transfer in complex molecular systems are discussed. (c) 2007 American Institute of Physics.

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A time-varying controllable fault-tolerant field associative memory model and the realization algorithms are proposed. On the one hand, this model simulates the time-dependent changeability character of the fault-tolerant field of human brain's associative memory. On the other hand, fault-tolerant fields of the memory samples of the model can be controlled, and we can design proper fault-tolerant fields for memory samples at different time according to the essentiality of memory samples. Moreover, the model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. And the fault-tolerant fields of the memory samples are full of the whole real space R-n. The simulation shows that the model has the above characters and the speed of associative memory about the model is faster.

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A design algorithm of an associative memory neural network is proposed. The benefit of this design algorithm is to make the designed associative memory model can implement the hoped situation. On the one hand, the designed model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. The result has improved the ones of some old associative memory neural network. On the other hand, the memory samples are in the centers of the fault-tolerant. In average significance the radius of the memory sample fault-tolerant field is maximum.

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AlGaN/GaN npn heterojunction bipolar transistor structures were grown by low-pressure MOCVD. Secondary ion mass spectroscopy (SIMS) measurements were carried out to study the Mg memory effect and redistribution in the emitter-base junction. The results indicated that there is a Mg-rich film formed in the ongrowing layer after the Cp2Mg source is switched off. The Mg-rich film can be confined in the base section by switching off the Cp2Mg source for appropriate time before the end of base growth. Low temperature growth of the undoped GaN spacer suppresses the Mg redistribution from Mg rich film. The delay rate of the Mg profile in sample C with spacer growing in low temperature is about 56 nm/decade, which becomes sharper than 80 nm/decade of the samples A and B without low temperature spacer. (C) 2005 Elsevier Ltd. All rights reserved.

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We report a new type of photonic memory cell based on a semiconductor quantum dot (QD)-quantum well (QW) hybrid structure, in which photo-generated excitons can be decomposed into separated electrons and holes, and stored in QW and QDs respectively. Storage and retrieval of photonic signals are verified by time-resolved photoluminescence experiments. A storage time in excess of 100ms has been obtained at a temperature of 10 K while the switching speed reaches the order of ten megahertz.

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The in-situ p-type doping of 4H-SiC grown on off-oriented (0001) 4H-SiC substrates was performed with trimethylaluminum (TMA) and/or diborane (B2H6) as the dopants. The incorporations of Al and B atoms and their memory effects and the electrical properties of p-type 4H-SiC epilayers were characterized by secondary ion mass spectroscopy (SIMS) and Hall effect measurements, respectively. Both Al- and B-doped 4H-SiC epilayers were p-type conduction. It was shown that the profiles of the incorporated boron and aluminum concentration were in agreement with the designed TMA and B2H6 flow rate diagrams. The maximum hole concentration for the Al doped 4H-SiC was 3.52x10(20) cm(-3) with Hall mobility of about 1 cm(2)/Vs and resistivity of 1.6 similar to 2.2x10(-2) Omega cm. The heavily boron-doped 4H-SiC samples were also obtained with B2H6 gas flow rate of 5 sccm, yielding values of 0.328 Omega cm for resistivity, 5.3x10(18) cm(-3) for hole carrier concentration, and 7 cm(2)/VS for hole mobility. The doping efficiency of Al in SiC is larger than that of B. The memory effects of Al and B were investigated in undoped 4H-SiC by using SIMS measurement after a few run of doped 4H-SiC growth. It was clearly shown that the memory effect of Al is stronger than that of B. It is suggested that p-type 4H-SiC growth should be carried out in a separate reactor, especially for Al doping, in order to avoid the join contamination on the subsequent n-type growth. 4H-SiC PiN diodes were fabricated by using heavily B doped epilayers. Preliminary results of PiN diodes with blocking voltage of 300 V and forward voltage drop of 3.0 V were obtained.

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This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

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An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

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Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-06-07T01:33:41Z No. of bitstreams: 1 ApplPhysLett_96_213505.pdf: 1153920 bytes, checksum: 69931d8deb797813dd478b5dd0e292c0 (MD5)