On the performance analysis and design of a novel shared-layer integrated devices using RCE-p-i-n-PD/SHBT - art. no. 67820J

We have explored the shared-layer integration fabrication of an resonant-cavity-enhanced p-i-n photodector (RCE- p-i-n-PD) and a single heterojunction bipolar transistor (SHBT) with the same epitaxy grown layer structure. MOCVD growth of the different layer structure for the GaAs based RCE- p-i-n-PD/SHBT require compromises to obtain the best performance of the integrated devices. The SHBT is proposed with super-lattice in the collector, and the structure of the base and the collector of the SHBT is used for the RCE. Up to now, the DC characteristics of the integrated device have been obtained.

Design and performance of monolithic integrated electro-absorption modulated distributed feedback laser - art. no. 67820Y

High performance InGaAsP/InGaAsP strained compensated multiple-quantum-well (MQW) electroabsorption modulators (EAM) monolithically integrated with a DFB laser diode have been designed and realized by ultra low metal-organic vapor phase epitaxy (MOVPE) based on a novel butt joint scheme. The optimization thickness of upper SCH layer for DFB and EAM was obtained of the proposed MQW structure of the EAM through numerical simulation and experiment. The device containing 250(mu m) DFB and 170(mu m) EAM shows good material quality and exhibits a threshold current of 17mA, an extinction ratio of higher than 30 dB and a very high modulation efficiency (12dB/V) from 0V to 1V. By adopting a high-mesa ridge waveguide and buried polyimide, the capacitance of the modulator is reduced to about 0.30 pF corresponding to a 3dB bandwidth more than 20GHz.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

An integrated optical receiver in MS/RF CMOS process

A monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance.

SOI optical switch matrix integrated with spot size converter (SSC) and total internal reflection (TIR) mirrors

SOI (Silicon on Insulator) based photonic devices has attracted more and more attention in the recent years. Integration of SOI optical switch matrix with isolating grooves, total internal reflection (TIR) mirrors and spot size converter (SSC) was studied. A folding re-arrangeable non-blocking 4x4 optical switch matrix and a blocking 16x16 matrix with TIR mirrors and SSC were fabricated on SOI wafer. The performaces, including extinction ratio and the crosstalk, are better than before. The insertion loss and the polarization dependent loss (PDL) at 1.55 mu m increase slightly with longer device length, more bend and intersecting waveguides. The insertion losses decrease 2 similar to 3 dB when anti-reflection films are added in the ends of the devices. The rise and fall times of the devices are 2.1 mu s and 2.3 mu s, respectively.

A low power integrated CMOS transmitter for BCI system

The prototype wafer of a low power integrated CMOS Transmitter for short-range biotelemetry application has been designed and fabricated, which is prospective to be implanted in the human brain to transfer the extracted neural information to the external computer. The transmitter consists of five parts, a bandgap current regulator, a ring oscillator, a buffer, a modulator and a power transistor. High integration and low power are the most distinct criteria for such an implantable integrated circuit. The post-simulation results show that under a 3.3 V power supply the transmitter provides 100.1 MHz half-wave sinusoid current signal to drive the off-chip antenna, the output peak current range is -0.155 mA similar to 1.250 mA, and on-chip static power dissipation is low to 0.374 mW. All the performances of the transmitter satisfy the demands of wireless real-time BCI system for neural signals recording and processing.

Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.