A simple route of morphology control and structural and optical properties of ZnO grown by metal-organic chemical vapour deposition

Employing the metal-organic chemical vapour deposition (MOCVD) technique, we prepare ZnO samples with different morphologies from the film to nanorods through conveniently changing the bubbled diethylzinc flux (BDF) and the carrier gas flux of oxygen (OCGF). The scanning electron microscope images indicate that small BDF and OCGF induce two-dimensional growth while the large ones avail quasi-one-dimensional growth. X-ray diffraction (XRD) and Raman scattering analyses show that all of the morphology-dependent ZnO samples are of high crystal quality with a c-axis orientation. From the precise shifts of the 2 theta. locations of ZnO (002) face in the XRD patterns and the E-2(high) locations in the Raman spectra, we deduce that the compressive stress forms in the ZnO samples and is strengthened with the increasing BDF and OCGF. Photoluminescence spectroscopy results show all the samples have a sharp ultraviolet luminescent band without any defects-related emission. Upon the experiments a possible growth mechanism is proposed.

A simple ac bridge for detecting small resistance change

A simple ac resistance bridge is proposed. The stability of the design is better than 10(-6), which is especially suitable for detecting tiny changes of resistance. An example of magnetoresistance measurement for a 220 nm Au film shows the good performance of the bridge. (C) 2009 American Institute of Physics. [DOI: 10.1063/1.3202284]

Pump-Suppressed Nondegenerate Four-Wave Mixing in a Highly Nonlinear Photonic Crystal Fiber Sagnac Loop

We propose a configuration for suppressing pumps in a broad- and flat-hand tunable nondegenerate four-wave mixing (FWM) wavelength converter. The signal and pumps are coupled into a highly nonlinear photonic crystal fiber symmetrical Sagnac loop. After the FWM wavelength conversion in the loop, the idler is separated from the pumps without a filter. In our experiment, a flat wavelength conversion bandwidth of 36 rim, conversion efficiency of-11 dB., pump-to-signal suppression ratio of 48 dB, and idler-to-pump suppression ratio of 15 dB are achieved.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Simple method for estimating minimum bend radii of SOI single mode curved rib waveguides

A simple method based on the effective index method was used to estimate the minimum bend radii of curved SOI waveguides. An analytical formula was obtained to estimate the minimum radius of curvature at which the mode becomes cut off due to the side radiative loss.

Carrier capture into InAs/GaAs quantum dots detected by a simple degenerate pump-probe technique

We demonstrate that the carrier capture and relaxation processes in InAs/GaAs quantum dots can be detected by a simple degenerate pump-probe technique. We have observed a rising process in the transient reflectivity, following the initial fast relaxation in a GaAs matrix, and assigned this rising process to the carrier capture from the GaAs barriers to the InAs layers. The assignment was modeled using the Kramers-Kronig relations. The capture time was found to depend strongly on the InAs layer thickness as well as on the excitation density and photon energy. (C) 2000 Elsevier Science Ltd. All rights reserved.

Simple reflection technique for measuring the linear electro-optic coefficient of the polymer thin films

The simple reflection technique is usually used to measure the linear electro-optic (EO) coefficient (Pockels coefficient) in the development of EO polymer thin films. But there are some problems in some articles in the determination of the phase shift between the s and p light modes of a laser beam waveguided into the polymer film while a modulating voltage is applied across the electrodes, and different expressions for the linear EO coefficient measured have been given in these articles. In our research, more accurate expression of the linear EO coefficient was deduced by suitable considering the phase shift between the s and p light modes. The linear EO coefficients of several polymer thin films were measured by reflection technique, and the results of the Linear EO coefficient calculated by different expressions were compared. The limit of the simple reflection technique for measuring the linear EO coefficient of the polymer thin films was discussed.

Ground-state properties of an artificial molecule: a simple model calculation for the double quantum dot

The ground state of a double quantum-dot structure is studied by a simplified Anderson-type model. Numerical calculations reveal that the ground-state level of this artificial molecule increases with the increasing single particle level of the dot, and also increases with the decreasing transfer integrals. We show the staircase feature of the electron occupation and the properties of the ground-state eigenvector by varying the;single particle level of the dot.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

A simple method to realize large-bandwidth and high-efficiency wavelength conversion in Si waveguide

Submitted by 阎军 (yanj@red.semi.ac.cn) on 2010-06-04T07:06:36Z No. of bitstreams: 1 A simple method to realize large-bandwidth and high-efficiency wavelength conversion in Si waveguide.pdf: 277035 bytes, checksum: ca7e272b2286b305d385825417857f21 (MD5)

a simple but effective improvement to the plumb-line algorithm

Emporiki Bank; Microsoft; Alpha Bank