134 resultados para Laserspektroskopie, ESR, Bismut, lithiumähnlich, QED-Test


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本论文侧重用现场及非现场的光谱电化学方法研究导电聚合物的电聚合过程及聚合物薄膜修饰甲极的氧化-还原行为。用现场的ESR电化学研究了二苯胺的电聚合过程;用现场的可见光谱电化学及非现场的低温ESR研究了同多酸及杂多酸掺杂的聚吡咯薄膜的氧化-还原行为,同时对磷铜酸掺杂的聚吡咯薄膜电极的制备方法及聚合物薄膜修饰电极的电催化性能作了较为细致研究。

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A thermal model for concentrator solar cells based on energy conservation principles was designed. Under 400X concentration with no cooling aid, the cell temperature would get up to about 1200℃.Metal plates were used as heat sinks for cooling the system, which remarkably reduce the cell temperature. For a fixed concentration ratio, the cell temperature reduced as the heat sink area increased. In order to keep the cell at a constant temperature, the heat sink area needs to increase linearly as a function of the concentration ratio. GaInP/GaAs/Ge triple-junction solar cells were fabricated to verify the model. A cell temperature of 37℃ was measured when using a heat sink at 400X concentratration.

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With the principles of microwave circuits and semiconductor device physics, two microwave power device test circuits combined with a test fixture are designed and simulated, whose properties are evaluated by a parameter network analyzer within the frequency range from 3 to 8GHz. The simulation and experimental results verify that the test circuit with a radial stub is better than that without. As an example, a C-band AlGaN/GaN HEMT microwave power device is tested with the designed circuit and fixture. With a 5.4GHz microwave input signal, the maximum gain is 8.75dB, and the maximum output power is 33.2dBm.

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The open-short-load (OSL) method is very simple and widely used, for one-port test fixture calibration. In this paper, this method. is extended to the two-port calibration of test fixtures for the first time. The problem of phase uncertainty arising in this application has been solved. The comparison between our results and those obtained with the short-open-load-thru (SOLT) method shows that the method established is accurate enough for practical applications.

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The problem of frequency limitation arising in calibration of the test fixtures is investigated in this paper. It is found that at some frequencies periodically, the accuracy of the methods becomes very low, and. the denominators of the expressions of the required S-parameters approach zero. This conclusion can be drawn whether-the test fixtures, are symmetric or not. A good agreement between theory and experiment is obtained.

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Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18x18 bits Booth Coding-Wallace Tree multiplier has been designed with full custom approach with 0.61 m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more areas and 24.4% more delay time, while the fault coverage reaches to 95%.

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