Zn-doped InGaAs Base Heterojunction Bipolar Transistors Grown by Low Pressure Metal Organic Chemical Vapor Deposition

High performance InP/InGaAs heterojunction bipolar transistors(HBTs) have been widely used in high-speed electronic devices and optoelectronic integrated circuits. InP-based HBTs were fabricated by low pressure metal organic chemical vapor deposition(MOCVD) and wet chemical etching. The sub-collector and collector were grown at 655 ℃ and other layers at 550 ℃. To suppress the Zn out-diffusion in HBT, base layer was grown with a 16-minute growth interruption. Fabricated HBTs with emitter size of 2.5×20 μm~2 showed current gain of 70~90, breakdown voltage(BV_(CE0))>2 V, cut-off frequency(f_T) of 60 GHz and the maximum relaxation frequency(f_(MAX)) of 70 GHz.

A 10-GHz Bandwidth Electroabsorption Modulated Laser by Ultra-Low-Pressure Selective Area Growth

A novel integration technique has been developed using band-gap energy control of InGaAsP/InGaAsP multiquantum-well (MQW) structures during simultaneous ultra-low-pressure (22 mbar) selective-area-growth (SAG) process in metal-organic chemical vapour deposition. A fundamental study of the controllability of band gap energy by the SAG method is performed. A large band-gap photoluminescence wavelength shift of 83nm is obtained with a small mask width variation (0-30μm). The method is then applied to fabricate an MQW distributed-feedback laser monolithically integrated with an electroabsorption modulator. The experimental results exhibit superior device characteristics with low threshold of 19mA, over 24 dB extinction ratio when coupled into a single mode fibre. More than 10 GHz modulation bandwidth is also achieved, which demonstrates that the ultra-low-pressure SAG technique is a promising approach for high-speed transmission photonic integrated circuits.

Space-grown SI-GaAs and its application

A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-travelling furnace under microgravity. The crystal was characterized systematically and was used in fabricating low noise field effect transistors and analogue switch integrated circuits by the direct ion-implantation technique. All key electrical properties of these transistors and integrated circuits have surpassed those made from conventional earth-grown gallium arsenide. This result shows that device-grade space-grown semiconducting single. crystal has surpassed the best. terrestrial counterparts. Studies on the correlation between SI-GaAs wafers and the electronic devices and integrated circuits indicate that the characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry.

A semiconductor laser suitably fabricated by planar technology

The semiconductor microlasers with an equilateral triangle resonator which can be fabricated by dry etching technique from the laser wafer of the edge emitting laser, are analyzed by FDTD technique and rate equations. The results show that ETR microlaser is suitable to realize single mode operation. By connecting an output waveguide to one of the vertices of the ETR, we still can get the confined modes with high quality factors. The EM microlasers are potential light sources for photonic integrated circuits.

Multiple quantum well self electro-optic effect devices for optoelectronic smart pixels

The investigations on GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays for optoelectronic smart pixels are reported. The hybrid integration of GaAs/AlGaAs multiple quantum well devices flip-chip bonding directly over 1 mu m silicon CMOS circuits are demonstrated. The GaAs/AlGaAs multiple quantum well devices are designed for 850nm operation. The measurement results under applied biases show the good optoelectronic characteristics of elements in SEED arrays. The 4x4 optoelectronic crossbar structure consisting of hybrid CMOS-SEED smart pixels have been designed, which could be potentially used in optical interconnects for multiple processors.

Space grown semi-insulating gallium arsenide single crystal and its application

Low noise field effect transistors and analogue switch integrated circuits (ICs) have been fabricated in semi-insulating gallium arsenide (SI-GaAs) wafers grown in space by direct ion-implantation. The electrical behaviors of the devices and the ICs have surpassed those fabricated in the terrestrially grown SI-GaAs wafers. The highest gain and the lowest noise of the transistors made from space-grown SI-GaAs wafers are 22.8 dB and 0.78 dB, respectively. The threshold back-gating voltage of the ICs made from space-grown SI-GaAs wafers is better than 8.5 V The con-elation between the characterizations of materials and devices is studied systematically. (C) 2002 COSPAR. Published by Elsevier Science Ltd. All rights reserved.

High-mobility pentacene thin-film transistors with copolymer-gate dielectric

Pentacene thin-film transistors have been obtained using polymethyl-methacrylate-co-glyciclyl-methacrylate (PNIMA-GMA) as the gate dielectric. The optimum active layer thickness in thin-film transistors (OTFTs) was investigated. The present devices show a wide operation voltage range. The on/off current ratio is as high as 10(5). In linear region (V-DS = -2V), the field-effect mobility of device increases with the increase in gate field at low-voltage region (V-G < - 20 V), and a mobility of 0.33 cm(2)/Vs can be obtained when V-G > 20 V. In saturation region, the mobility increases linearly with the gate field, and a high mobility of 1.14 cm(2)/Vs can be obtained at V-G = -95V. The influence of voltage on mobility of device was investigated.

Bottom-contact organic field-effect transistors having low-dielectric layer under source and drain electrodes

An organic thin-film transistor (OTFT) having a low-dielectric polymer layer between gate insulator and source/drain electrodes is investigated. Copper phthalocyanine (CuPc), a well-known organic semiconductor, is used as an active layer to test performance of the device. Compared with bottom-contact devices, leakage current is reduced by roughly one order of magnitude, and on-state current is enhanced by almost one order of magnitude. The performance of the device is almost the same as that of a top-contact device. The low-dielectric polymer may play two roles to improve OTFT performance. One is that this structure influences electric-field distribution between source/drain electrodes and semiconductor and enhances charge injection. The other is that the polymer influences growth behavior of CuPc thin films and enhances physical connection between source/drain electrodes and semiconductor channel. Advantages of the OTFT having bottom-contact structure make it useful for integrated plastic electronic devices.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

Fabrication of a novel silica PLC hybrid integrated triplexer

A new-style silica planar lightwave circuit (PLC) hybrid integrated triplexer, which can demultiplex 1490-nm download data and 1550-nm download analog signals, as well as transmit 1310-nm upload data, is presented. It combines SiO2 arrayed waveguide gratings (AWGs) with integrated photodetectors (PDs) and a high performance laser diode (LD). The SiO2 AWGs realize the three-wavelength coarse wavelength-division multiplexing (CWDM). The crosstalk is less than 40 dB between the 1490- and 1550-nm channels, and less than 45 dB between 1310- and 1490- or 1550-nm channels. For the static performances of the integrated triplexer, its upload output power is 0.4 mW, and the download output photo-generated current is 76 A. In the small-signal measurement, the upstream 3-dB bandwidth of the triplexer is 4 GHz, while the downstream 3-dB bandwidths of both the analog and digital sections reach 1.9 GHz.