A novel butt-joint scheme for the preparation of electro-absorptive lasers

A 1.55 mu m InGaAsP/InGaAsP multiple-quantum-well electro-absorption modulator (EAM) monolithically integrated with a distributed feedback laser (DFB) diode has been realized based on a novel butt-joint scheme by ultra-low metal-organic vapour phase epitaxy for the first time. The threshold current of 25 mA and an extinction ratio of more than 30 dB are obtained by using the novel structure. The beam divergence angles at the horizontal and vertical directions are as small as 19.3 degrees x 13 degrees, respectively, without a spot-size converter by undercutting the InGaAsP active region. The capacitance of the ridge waveguide device with a deep mesa buried by polyimide was reduced down to 0.30 pF.

Fabrication and optical optimization of spot-size converters with strong cladding layers

A silicon-on-insulator (SOI) optical fiber-to-waveguide spot-size converter (SSC) overlaid with specially treated silica is investigated for integrated optical circuits. Unlike the conventional process of simply depositing the hot silica on silicon waveguides, two successive layers of silicon dioxide were grown on etched SSC structures by PECVD (plasma-enhanced chemical vapor deposition). The two layers have 0.8% index contrast and supply stronger cladding for an incident light beam. Additionally, this process is able to reduce the effective refractive index of the input mode to less than 1.47 (extremely close to that of the fiber), substantially weakening the unwanted back reflection. Exploiting this technology, it was demonstrated that the SSC showed a theoretical low mode mismatch loss of 1.23 dB for a TE-like mode and has an experimental coupling efficiency of 66%.

Pump-Suppressed Nondegenerate Four-Wave Mixing in a Highly Nonlinear Photonic Crystal Fiber Sagnac Loop

We propose a configuration for suppressing pumps in a broad- and flat-hand tunable nondegenerate four-wave mixing (FWM) wavelength converter. The signal and pumps are coupled into a highly nonlinear photonic crystal fiber symmetrical Sagnac loop. After the FWM wavelength conversion in the loop, the idler is separated from the pumps without a filter. In our experiment, a flat wavelength conversion bandwidth of 36 rim, conversion efficiency of-11 dB., pump-to-signal suppression ratio of 48 dB, and idler-to-pump suppression ratio of 15 dB are achieved.

Electroabsorption-Modulated DFB laser Integrated.With dual-core spot-size converters

A 1.55-mu m single shallow ridge electroabsorptionmodulated distributed feedback laser that is monolithically integrated with a buried-ridge-stripe dual-core spot-size converter (SSC) at the input and output ports was fabricated by combining selective area growth, quantum-well intermixing, and dual-core integration techniques simultaneously. These devices exhibit a threshold current of 34 mA, a side mode suppression ratio of 38.0 dB, a 3-dB modulation bandwidth of 11.0 GHz, and a modulator extinction ratio of 25.0 dB dc. The output beam divergence angles of the SSC in the horizontal and vertical directions are as small as 7.3 degrees x 18 degrees, respectively, resulting in 3.2-dB coupling loss with a cleaved single-mode optical fiber.

Submicrosecond rearrangeable nonblocking silicon-on-insulator thermo-optic 4 X 4 switch matrix

A rearrangeable nonblocking silicon-on-insulator-based thermo-optic 4 X 4 switch matrix is designed and fabricated. A spot-size converter is integrated to reduce the insertion loss, and a new driving circuit is designed to improve the response speed. The insertion loss is less than 10 dB, and the response time is 950 us. (c) 2007 Optical Society of America

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Semiconductor optical amplifier optical gate with graded strained bulk-like active structure

A novel semiconductor optical amplifier (SOA) optical gate with a graded strained bulk-like active structure is proposed. A fiber-to-fiber gain of 10 dB when the coupling loss reaches 7 dB/factet and a polarization insensitivity of less than 0.9 dB for multiwavelength and different power input signals over the whole operation current are obtained. Moreover, for our SOA optical gate, a no-loss current of 50 to 70 mA and an extinction ratio of more than 50 dB are realized when the injection current is more than no-loss current, and the maximum extinction ratio reaches 71 dB, which is critical for crosstalk suppression. (C) 2003 society of Photo-Optical Instrumentation Engineers.

Investigation progress on key photonic integration for application in optical communication network

Proceeding from the consideration of the demands from the functional architecture of high speed, high capacity optical communication network, this paper points out that photonic integrated devices, including high speed response laser source, narrow band response photodetector high speed wavelength converter, dense wavelength multi/demultiplexer, low loss high speed response photo-switch and multi-beam coupler are the key components in the system. The, investigation progress in the laboratory will be introduced.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

Investigations on oxide-free InGaAlAs waveguides grown by narrow stripe selective MOVPE

Oxide-free InGaAlAs waveguides have been grown on the InP substrates patterned with pairs of SiO2 mask stripes using narrow stripe selective MOVPE. The mask stripe width is varied from 0 to 40 pm, while the window region width between a pair of mask stripes is fixed at 1.5, 2.5 and 3.5 mu m, respectively. Smooth surface s and flat interfaces are obtained in the selectively grown InQaAlAs waveguides. There exhibit strong dependences of the thickness enhancement ratio and the photoluminescence (PL) spectrum on the mask stripe width and the window region width for the InGaAlAs wavegwdes. A large PL peak wavelength shift of 79 nm and a PL full width of at half maximum (FWHM) of less than 64 meV are obtained simultaneously. Some possible interpretations for our investigations are presented by considering both the migration effect from a masked region (MMR) and the lateral vapor diffusion effect (LVD).

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

SOA-based polarity-preserving all-optical wavelength conversion at 80Gbit/s: Wide conversion range, well dynamic characteristics and polarization insensitive

This letter presents the effective design of a tunable 80 Gbit/s wavelength converter with a simple configuration consisting of a single semiconductor optical amplifier (SOA) and an optical bandpass filter (OBPF). Based on both cross-gain and cross-phase modulation in SOA, the polarity-preserved, ultrafast wavelength conversion is achieved by appropriately filtering the blue-chirped spectral component of a probe light. Moreover, the experiments are carried out to investigate into the wavelength tunability and the maximum tuning range of the designed wavelength converter. Our results show that a wide wavelength conversion range of nearly 35 nm is achieved with 21-nm downconversion and 14-nm upconversion, which is substantially limited by the operation wavelength ranges of a tunable OBPF and a tunable continuous-wave laser in our experiment. We also exploited the dynamics characteristics of the wavelength converter with variable input powers and different injection current of SOA. (C) 2008 Wiley Periodicals, Inc.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

A novel polarization-insensitive semiconductor optical amplifier structure with large 3dB bandwidth

A novel approach to achieving a polarization-insensitive semiconductor optical amplifier is presented. The active layer consists of graded tensile strained bulk-like structure. which can not only enhance TM mode material gain and further realize polarization-insensitivity, but also get a large 3dB bandwidth due to different strain introduced into the active layer. 3dB bandwidth more than 40nm. 65nm has been obtained in die experiment and theory, respectively. The characteristics of such polarization insensitive structure have been analyzed, The influence of the amount of strain and of the thickness of strain layer on the polarization insensitivity has been discussed.