线粒体D-loop序列变异与东方鲀属鱼类系统发育

东方鲀属的红鳍东方鲀(Takifugu rubripes)是后基因组时代的一种重要模式生物。本研究中,利用东方鲀属11种鱼类(18尾)的D-loop基因序列,对东方鲀属鱼类的系统发育关系进行研究。经序列比对排定后,分析中D-loop序列有841个位点,其中395个位点为可变位点,267个位点为系统发育信息位点。分别采用邻接法(NJ)、最大简约法(MP)、最大似然法(ML)和贝叶斯方法构建了分子系统树。研究结果表明:(1)东方鲀属鱼类为一单系类群;(2)由横纹东方鲀(T. oblongus)和铅点东方鲀(T

线粒体DNA d-loop序列变异与鳅鮀亚科鱼类系统发育

对鳅鮀亚科(Gobiobotinae)2个属8个种10个个体线粒体控制区d-loop全序列进行了测定.以(鱼丹)亚科斑马鱼为外类群,对鳅鮀及鲤科(Cyprinidae)一些亚科代表种鱼类进行了系统发育分析.结果显示,鳅鮀鱼类是一个单系类群,与鮈和细鲫有较近的亲缘关系.从系统发育的角度看,鳅鮀亚科应归属于鮈亚科(Gobioninae).研究结果支持鳅鮀亚科分为异鳔鳅鳅属(Xenophyso-gobio)和鳅鮀属(Gobiobtia).

Sonar gain control in echolocating finless porpoises (Neophocaena phocaenoides) in an open water (L)

Source levels of echolocating free-ranging Yangtze finless porpoise (Neophocaena phocaenoides asiaeorientalis) were calculated using a range estimated by measuring the time delays of the signals via the surface and bottom reflection paths to the hydrophone, relative to the direct signal. Peak-to-peak source levels for finless porpoise were from 163.7 to 185.6 dB re:1 mu Pa. The source levels are highly range dependent and varied approximately as a function of the one-way transmission loss for signals traveling from the animals to the hydrophone. (c) 2006 Acoustical Society of America.

Mitochondrial d-loop sequence variation and phylogeny of gobiobotine fishes

The mitochondrial DNA control region is amplified and sequenced from 8 genera and 10 species of gobiobotine fishes. The phylogenetic tree of Gobiobotinae and some representative species of other Cyprinid subfamilies obtained by the method of neighborhood joining, maximum likelihood and maximum parsimony with Danio rerio as an outgroup indicates that Gobiobotinae fishes are a monophyletic group which is close to Gobioninae subfamily. Gobiobotinae should be included into subfamily Gobioninae in terms of phylogenetic analysis. The research result supports that Gobiobotinae can be divided into genus Xenophysogobio and Gobiobotia. Xenophysogabio is the most primitive genera in the subfamily.

Degenerate four-wave mixing based all-optical wavelength conversion in a semiconductor optical amplifier and highly-nonlinear photonic crystal fiber parametric loop mirror

The idler is separated from the co-propagating pump in a degenerate four-wave mixing (DFWM) with a symmetrical parametric loop mirror (PALM), which is composed of two identical SOAs and a 70 m highly-nonlinear photonic crystal fiber (HN-PCF). The signal and pump are coupled into the symmetrical PALM from different ports, respectively. After the DFWM based wavelength conversion (WC) in the clockwise and anticlockwise, the idler exits from the signal port, while the pump outputs from its input port. Therefore, the pump is effectively suppressed in the idler channel without a high-speed tunable filter. Contrast to a traditional PALM, the DFWM based conversion efficiency is increased greatly, and the functions of the amplification and the WC are integrated in the smart SOA and HN-PCF PALM. (C) 2008 Elsevier B.V. All rights reserved.

Pump-Suppressed Nondegenerate Four-Wave Mixing in a Highly Nonlinear Photonic Crystal Fiber Sagnac Loop

We propose a configuration for suppressing pumps in a broad- and flat-hand tunable nondegenerate four-wave mixing (FWM) wavelength converter. The signal and pumps are coupled into a highly nonlinear photonic crystal fiber symmetrical Sagnac loop. After the FWM wavelength conversion in the loop, the idler is separated from the pumps without a filter. In our experiment, a flat wavelength conversion bandwidth of 36 rim, conversion efficiency of-11 dB., pump-to-signal suppression ratio of 48 dB, and idler-to-pump suppression ratio of 15 dB are achieved.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

Quantum transport from the perspective of quantum open systems

By viewing the non-equilibrium transport setup as a quantum open system, we propose a reduced-density-matrix based quantum transport formalism. At the level of self-consistent Born approximation, it can precisely account for the correlation between tunneling and the system internal many-body interaction, leading to certain novel behavior such as the non-equilibrium Kondo effect. It also opens a new way to construct time-dependent density functional theory for transport through large-scale complex systems. (c) 2006 Elsevier B.V. All rights reserved.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Fast Locking and High Accurate Current Matching Phase-Locked Loop

In this paper, a charge-pump based phase-locked loop (CPLL) that can achieve fast locking and tiny deviation is proposed and analyzed. A lock-aid circuit is added to achieve fast locking of the CPLL. Besides, a novel differential charge pump which has good current matching characteristics and a PFD with delay cell has been used in this PLL. The proposed PILL circuit is designed based on the 0.35um 2P4M CMOS process with 3.3V/5V supply voltage. HSPICE simulation shows that the lock time of the proposed CPLL can be reduced by over 72% in comparison to the conventional PILL and its charge pump sink and source current mismatch is only 0.008%.

A Fast-Locking Phase-Locked Loop Using a Seven-State Phase Frequency Detector

A seven-state phase frequency detector (S.S PFD) is proposed for fast-locking charge pump based phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be significantly reduced by using the seven-state PFD to inject more current into the loop filter. In this stage, the bandwidth of the PLL is increased or decreased to track the phase difference of the reference signal and the feedback signal. The proposed architecture is realized in a standard 0.35 mu m 2P4M CMOS process with a 3.3V supply voltage. The locking time of the proposed PLL is 1.102 mu s compared with the 2.347 mu s of the PLL based on continuous-time PFD and the 3.298 mu s of the PLL based on the pass-transistor tri-state PFD. There are 53.05% and 66.59% reductions of the locking time. The simulation results and the comparison with other PLLs demonstrate that the proposed seven-state PFD is effective to reduce locking time.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.