Electronic states of InAs verfically-assembled quantum disks in magnetic fields and two-electron quantum-disk qubit

We have studied the single-electron and two-electron vertically-assembled quantum disks in an axial magnetic field using the effective mass approximation. The electron interaction is treated accurately by the direct diagonalization of the Hamiltonian matrix. We calculate the six criergy levels of single-electron quantum disks and the two lowest energy levels of two-electron quantum disks in an axial magnetic field. The change of the magnetic field as an effective potential strongly modifies the electronic structures. leading to splittings and crossings between levels The results demonstrate the switching between the around states with the total spins S = 0 and S = 1. The switching results in a qubit allowed to fabricate by current growth techniques.

Influence of fluorine on radiation-induced charge trapping in the SIMOX buried oxides

Charge trapping in the fluorinated SIMOX buried oxides before and after ionizing radiation has been investigated by means of C-V characteristics. Radiation-induced positive charge trapping which results in negative shift of C-V curves can be restrained by implanting fluorine ions into the SIMOX buried oxides. Pre-radiation charge trapping is suppressed in the fluorinated buried oxides. The fluorine dose and post-implantation anneal time play a very important role in the control of charge trapping.

Radiation response of partially-depleted MOS transistors fabricated in the fluorinated SIMOX wafers

Ionizing radiation response of partially-depleted MOS transistors fabricated in the, fluorinated SIMOX wafers has been investigated. The experimental data show that the, radiation-induced threshold voltage shift of PMOSFETs and NMOSFETs, as well as the radiation-induced increase of off-state leakage current of NMOSFETs can be restrained by implanting fluorine ions into the buried oxide of SIMOX wafers.

A simulation model of body contact structure in PD SOI analogue circuit

As a solution of accurate simulation of the body effect in PD SOI analogue circuit, a simulation model of distributed body contact resistance and parasitical capacitance is presented. Based on this model, we have designed and simulated a sense amplifier that applied to V a 0.8um PD SOI 64K SRAM.

A silicon capacitive microphone based on oxidized porous silicon sacrificial technology

In this paper, a new capacitive microphone fabrication technology is proposed. It describes using the oxidized porous silicon sacrificial technology to make air gap and using KOH etching technique to make the backplate containing acoustic holes based on the principle that the heavy p(+)-doping silicon can be nearly etched in KOH solution. The innovation of the method is using oxidized porous silicon technology. The sensitivity of the fabricated microphone is from -55dB ( 1.78mV/Pa) to -45dB (5.6mV/Pa) in the frequency range of 500Hz to 25kHz. Its cut-off frequency is higher than 20kHz.

A practical package technique for FBG-based temperature independent sensor

A practical package technique for temperature independent Fiber Bragg grating sensor is proposed. A uniform strength cantilever with two FBG attached on the upper and lower surfaces was utilized as the key element. By detecting two wavelengths differential output, the applied force can be obtained and temperature effects can be eliminated. Experiment results show the sensor has linear response and output signal uctuates less than 12pm as temperature changes from -10 degrees C to 50 degrees C. The maximum thermal error is less than 0.3% of the full measurement range.

Structural optimizations of SOI-based single-mode rib waveguide bends

Effects of structure parameters on bend loss of rib silicon-on-insulator (Sol) bend waveguides have been analyzed by means of effective index method (EIM) and 2D bend loss formula. The simulation results indicate that the bend loss decreases with the increase of bend radius and waveguide width, as well as with the decrease of the step factor of the rib waveguide. Moreover, the optional structure parameters have been found when bend waveguides are single-mode.

A low power consumption thermo-optic variable optical attenuator based on SOI material

A SOI thenno-optic variable optical attenuator with U-grooves based on a multimode interference coupler principle is fabricated. The dynamic attenuation range is 0 to 29 dB; at the wavelength range between 1510 nm and 1610nm, and the maximum power consumption is only l30mW. Compared to the variable optical attenuator without U-groove, the maximum power consumption decreases more than 230mW

The effect of Fabry-Perot interference on the packaging of SOI-based optoelectronic devices

During the packaging of optoelectrome device, a problem always met is the instability of output power. The main effect causing this problem, Fabry-Perot interference, is discussed in this paper. Both theoretical analysis and experimental test are carried out and in good agreement. As an example of avoiding the disadvantage of Fabry-Perot interference, the packaging process of Silicon-on-Insulator (SOI) based Variable Optical Attenuator(VOA) is shown at last.

Improved diphasic nc-si/a-si : H I-layer materials using PECVD

Two series of films has been prepared by using a new regime of plasma enhanced chemical vapor deposition (PECVD) in the region adjacent to the phase transition from amorphous to crystalline state. The photoelectronic properties of the films have been investigated as a function of crystalline fraction. In comparison with typical a-Si:H, these diphasic films with a crystalline fraction less than 0.3 show a similar optical absorption coefficient, higher mobility life-time product ( LT) and higher stability upon light soaking. By using the diphasic nc-Si/a-Si films as the intrinsic layer, a p-i-n junction solar cell has been prepared with an initial efficiency of 9. 10 % and a stabilized efficiency of 8.56 % (AM 1.5, 100 mW/cm(2)).

Homoepitaxial growth and MOS structures of 4H-SiC on off oriented n-type (0001)Si-faces

Homoepitaxial growth of 4H-SiC on off-oriented n-type Si-face (0001) substrates was performed in a home-made hot-wall low pressure chemical vapor deposition (LPCVD) reactor with SiH4 and C2H4 at temperature of 1500 C and pressure of 20 Torr. The surface morphology and intentional in-situ NH3 doping in 4H-SiC epilayers were investigated by using atomic force microscopy (AFM) and secondary ion mass spectroscopy (SIMS). Thermal oxidization of 4H-SiC homoepitaxial layers was conducted in a dry O-2 and H-2 atmosphere at temperature of 1150 C. The oxide was investigated by employing x-ray photoelectron spectroscopy (XPS). 4H-SiC MOS structures were obtained and their C-V characteristics were presented.

Hetero-epitaxial growth of ZnO films on silicon by low-pressure metal organic chemical vapor deposition

Quality ZnO films were successfully grown on Si(100) substrate by low-pressure metal organic chemical vapor deposition method in temperature range of 300-500 degrees C using DEZn and N2O as precursor and oxygen source respectively. The crystal structure, optical properties and surface morphology of ZnO films were characterized by X-ray diffraction, optical refection and atomic force microscopy technologies. It was demonstrated that the crystalline structure and surface morphology of ZnO films strongly depend on the growth temperature.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

NEW TYPE OF SILICON MATERIAL WITH VERY HIGH-QUALITY SURFACE-LAYER ON INSULATING DEFECT LAYER

A new-type silicon material, silicon on defect layer (SODL) was proved to have a very high quality surface microstructure which is necessary for commercially feasible high-density very large scale integrated circuits (VLSI). The structure of the SODL material was viewed by transmission electron microscopy. The SODL material was also proved to have a buried defect layer with an insulating resistivity of 5.7 x 10(10) OMEGA-cm.