Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

AN EFFICIENT ITERATIVE DFT-BASED CHANNEL ESTIMATION FOR MIMO-OFDM SYSTEMS ON MULTIPATH CHANNELS

In this paper, an efficient iterative discrete Fourier transform (DFT) -based channel estimator with good performance for multiple-input and multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems such as IEEE 802.11n which retain some sub-carriers as null sub-carriers (or virtual carriers) is proposed. In order to eliminate the mean-square error (MSE) floor effect existed in conventional DFT-based channel estimators, we proposed a low-complexity method to detect the significant channel impulse response (CIR) taps, which neither need any statistical channel information nor a predetermined threshold value. Analysis and simulation results show that the proposed method has much better performance than conventional DFT-based channel estimators and without MSE floor effect.

Implantable Microsystem for Wireless Neural Recording Applications

A prototype microsystem is presented for wireless neural recording application. An inductive link was built for transcutaneous wireless power transfer and data transmission. Total 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 - 5 MHz with a distance of 0-10 mm. The integrated amplifiers were designed with a limited bandwidth for neural signals acquisition. The gain of 60 dB was obtained by preamplifier at 7 Hz - 3 KHz. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments with 0.374 - 2 mW power comsumption and a maximum data rate of 500 Kbps at 100 MHz. All the integrated circuits modules except the power recovery circuit were tested or stimulated under a 3.3 V power supply, and fabricated in standard CMOS processing.

Selective and lithography-independent fabrication of 20 nm nano-gap electrodes and nano-channels for nanoelectrofluidics applications

A new method has been developed to selectively fabricate nano-gap electrodes and nano-channels by conventional lithography. Based on a sacrificial spacer process, we have successfully obtained sub-100-nm nano-gap electrodes and nano-channels and further reduced the dimensions to 20 nm by shrinking the sacrificial spacer size. Our method shows good selectivity between nano-gap electrodes and nano-channels due to different sacrificial spacer etch conditions. There is no length limit for the nano-gap electrode and the nano-channel. The method reported in this paper also allows for wafer scale fabrication, high throughput, low cost, and good compatibility with modern semiconductor technology.

SIMULATION OF LATERAL CONFINEMENT IN VERY NARROW CHANNELS

A theoretical study is presented of the lateral confinement potential (CP) in the very narrow mesa channels fabricated in the conventional two-dimensional (2D) electron gas in GaAs-AlxGa1-xAs heterostructures. The ID electronic structures are calculated in the framework of the confinement potential: V(x) = m* omega0(2)x2/2 for Absolute value of x

VLSI architecture of a K-best detector for MIMO--OFDM wireless communication systems

The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

A Multi-Finger Si_(1-x)Ge_x/Si Heterojunction Bipolar Transistor for Wireless Power Amplifier Applications

A large area multi-finger configuration power SiGe HBT device(with an emitter area of about 880μm~2)was fabricated with 2μm double-mesa technology.The maximum DC current gain β is 214.The BV_(CEO) is up to 10V,and the BV_(CBO) is up to 16V with a collector doping concentration of 1×10~(17)cm~(-3) and collector thickness of 400nm.The device exhibits a maximum oscillation frequency f_(max) of 19.3GHz and a cut-off frequency f_T of 18.0GHz at a DC bias point of I_C=30mA and V_(CE)=3V.MSG(maximum stable gain)is 24.5dB,and U(Mason unilateral gain)is 26.6dB at 1GHz.Due to the novel distribution layout,no notable current gain fall-off or thermal effects are observed in the I-V characteristics at high collector current.

Design and Fabrication of Power Si1-xGex/Si Heterojunction Bipolar Transistor for Wireless Power Amplifier Applications

A multi-finger structure power SiGe HBT device （with an emitter area of about 166μm^2） is fabricated with very simple 2μm double-mesa technology. The DC current gain β is 144.25. The B-C junction breakdown voltage reaches 9V with a collector doping concentration of 1 × 10^17cm^-3 and a collector thickness of 400nm. Though our data are influenced by large additional RF probe pads, the device exhibits a maximum oscillation frequency fmax of 10.1GHz and a cut-off frequency fτ of 1.8GHz at a DC bias point of IC=10mA and VCE = 2.5V.