Fuzzy inferring mathematical morphology and optical implementation

Fuzzification is introduced into gray-scale mathematical morphology by using two-input one-output fuzzy rule-based inference systems. The fuzzy inferring dilation or erosion is defined from the approximate reasoning of the two consequences of a dilation or an erosion and an extended rank-order operation. The fuzzy inference systems with numbers of rules and fuzzy membership functions are further reduced to a simple fuzzy system formulated by only an exponential two-input one-output function. Such a one-function fuzzy inference system is able to approach complex fuzzy inference systems by using two specified parameters within it-a proportion to characterize the fuzzy degree and an exponent to depict the nonlinearity in the inferring. The proposed fuzzy inferring morphological operators tend to keep the object details comparable to the structuring element and to smooth the conventional morphological operations. Based on digital area coding of a gray-scale image, incoherently optical correlation for neighboring connection, and optical thresholding for rank-order operations, a fuzzy inference system can be realized optically in parallel. (C) 1996 Society of Photo-Optical Instrumentation Engineers.

Code conversion from signed-digit to complement representation based on look-ahead optical logic operations

We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to complement representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quarternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system. (C) 2001 Society of Photo-Optical Instrumentation Engineers.

东湖生态系统污染状况的FUZZY聚类分析

以水色、透明度、五日生化需氧量、总氮、总磷、悬浮物等感官的和生物学的6个参数为依据,用fuzzy聚类分析方法对武汉东湖生态系统的污染状况进行了分析研究,所获得的结果与实际情况相符。同时也简单地介绍和讨论了用于生态学的fuzzy聚类分析的一般方法。

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Method for improving classification performance of neural network based on fuzzy input and network inversion

In order to effectively improve the classification performance of neural network, first architecture of fuzzy neural network with fuzzy input was proposed. Next a cost function of fuzzy outputs and non-fuzzy targets was defined. Then a learning algorithm from the cost function for adjusting weights was derived. And then the fuzzy neural network was inversed and fuzzified inversion algorithm was proposed. Finally, computer simulations on real-world pattern classification problems examine the effectives of the proposed approach. The experiment results show that the proposed approach has the merits of high learning efficiency, high classification accuracy and high generalization capability.

Coalition and distribution in fuzzy dynamic supply chain systems

In this paper, two models of coalition and income's distribution in FSCS (fuzzy supply chain systems) are proposed based on the fuzzy set theory and fuzzy cooperative game theory. The fuzzy dynamic coalition choice's recursive equations are constructed in terms of sup-t composition of fuzzy relations, where t is a triangular norm. The existence of the fuzzy relations in FSCS is also proved. On the other hand, the approaches to ascertain the fuzzy coalition through the choice's recursive equations and distribute the fuzzy income in FSCS by the fuzzy Shapley values are also given. These models are discussed in two parts: the fuzzy dynamic coalition choice of different units in FSCS; the fuzzy income's distribution model among different participators in the same coalition. Furthermore, numerical examples are given aiming at illustrating these models., and the results show that these models are feasible and validity in FSCS.

Photonic switch and NOT logic gate based on the hybrid integration of a GaAsVCSEL and a GaAs MISS

The hybrid integrated photonic switch and not logic gate based on the integration of a GaAs VCSEL (Vertical Cavity Surface Emitting Lasers) and a MISS (Metal-Insulator-Semiconductor Switches) device are reported. The GaAs VCSEL is fabricated by selective etching and selective oxidation. The Ultra-Thin semi-Insulating layer (UTI) of the GaAs MISS is formed by using oxidation of A1As that is grown by MBE. The accurate control of UTI and the processing compatibility between VCSEL and MISS are solved by this procedure. Ifa VCSEL is connected in series with a MISS, the integrated device can be used as a photonic switch, or a light amplifier. A low switching power (10 mu W) and a good on-off ratio (17 dB contrast) have been achieved. If they are connected in parallel, they perform a photonic NOT gate operation.

Monostable-Bistable Transition Logic Element (MOBILE) Model for Single-Electron Transistors

The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators

Submitted by 张磊 (zhanglei@semi.ac.cn) on 2010-06-03T13:47:18Z No. of bitstreams: 1 Directed XOR_XNOR.pdf: 556366 bytes, checksum: c67167a8648c1242c1eec35d6cca24f6 (MD5)