LSIS-III VLSI CAD 系统集成的研究

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

function definition language fdl and its implementation

A Function Definition Language (FDL) is presented. Though designed for describing specifications, FDL is also a general-purpose functional programming language. It uses context-free language as data type, supports pattern matching definition of functions, offers several function definition forms, and is executable. It is shown that FDL has strong expressiveness, is easy to use and describes algorithms concisely and naturally. An interpreter of FDL is introduced. Experiments and discussion are included.

一种通用神经网络处理机设计及其VLSI集成化讨论

于2010-11-23批量导入

Architecture research and hardware implementation on simplified neural computing system for face identification

This paper describes a special-purpose neural computing system for face identification. The system architecture and hardware implementation are introduced in detail. An algorithm based on biomimetic pattern recognition has been embedded. For the total 1200 tests for face identification, the false rejection rate is 3.7% and the false acceptance rate is 0.7%.

高性能全流水线可控参数JPEG-LS编码器实现

提出了一种高性能的JPEG-LS无损/近无损图像压缩算法VLSI实现结构.通过对JPEG-LS算法瓶颈的分析,针对算法中不利于流水线实现的场景缓存部分,采用了一种信号量集机制避免流水线等待.全流水线结构保证了算法实现可以满足高速图像传感器系统的吞吐量需求.同时通过高度参数化的设计,系统可以动态调整和优化算法参数,使压缩效果和效率适应不同的运行环境.算法在FPGA平台通过验证,并得到了接近甚至超过其他A-SIC实现的性能.