54 resultados para Maximal Compact Frames


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For the first time to our knowledge, the laser performance of Yb3+, Na+-codoped CaF2 single crystals was demonstrated. Self-Q-switched laser operation at 1050nm was observed for 976 nm diode pumping at room temperature. On 5 W of incident power, the repetition rate and width of the self-Q-switched pulses reached 28 kHz and 1.5 mu s, respectively. A maximal slope efficiency of 20.3% and minimal threshold absorbed pump power of 30 mW were respectively achieved with different output couplers, showing the promising application of Yb3+, Na+-codoped CaF2 crystals as compact and efficient solid-state lasers. (C) 2005 Optical Society of America.

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Protein tyrosine phosphatases (PTPs) are comprised of two superfamilies, the phosphatase I superfamily containing a single low-molecular-weight PTP (lmwPTP) family and the phosphatase II superfamily including both the higher-molecular-weight PTP (hmwPTP) and the dual-specificity phosphatase (DSP) families. The phosphatase I and H superfamilies are often considered to be the result of convergent evolution. The PTP sequence and structure analyses indicate that lmwPTPs, hmwPTPs, and DSPs share similar structures, functions, and a common signature motif, although they have low sequence identities and a different order of active sites in sequence or a circular permutation. The results of this work suggest that lmwPTPs and hmwPTPs/DSPs are remotely related in evolution. The earliest ancestral gene of PTPs could be from a short fragment containing about 90similar to120 nucleotides or 30similar to40 residues; however, a probable full PTP ancestral gene contained one transcript unit with two lmwPTP genes. All three PTP families may have resulted from a common ancestral gene by a series of duplications, fusions, and circular permutations. The circular permutation in PTPs is caused by a reading frame difference, which is similar to that in DNA methyltransferases. Nevertheless, the evolutionary mechanism of circular permutation in PTP genes seems to be more complicated than that in DNA methyltransferase genes. Both mechanisms in PTPs and DNA methyltransferases can be used to explain how some protein families and superfamilies came to be formed by circular permutations during molecular evolution.

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We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

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We propose and simulate a new kind of compact polarizing beam splitter (PBS) based on a photonic crystal ring resonator (PCRR) with complete photonic bandgaps. The two polarized states are separated far enough by resonant and nonresonant coupling between the waveguide modes and the microring modes. Some defect holes are utilized to control the beam propagation. The simulated results obtained by the finite-difference time-domain method show that high transmission (over 95%) is obtained and the polarization separation is realized with a length as short as 3.1 mu m. The design of the proposed PBS can be flexible, thanks to the advantages of PCRRs.

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A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.

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In this paper a compact polarization beam splitter based on a deformed photonic crystal directional coupler is designed and simulated. The transverse-electric (TE) guided mode and transverse-magnetic (TM) guided mode are split due to different guiding mechanisms. The effect of the shape deformation of the air holes on the coupler is studied. It discovered that the coupling strength of the coupled waveguides is strongly enhanced by introducing elliptical airholes, which reduce the device length to less than 18.5 mu m. A finite-difference time-domain simulation is performed to evaluate the performance of the device, and the extinction ratios for both TE and TM polarized light are higher than 20 dB.

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This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

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This paper proposes compact adders that are based on non-binary redundant number systems and single-electron (SE) devices. The adders use the number of single electrons to represent discrete multiple-valued logic state and manipulate single electrons to perform arithmetic operations. These adders have fast speed and are referred as fast adders. We develop a family of SE transfer circuits based on MOSFET-based SE turnstile. The fast adder circuit can be easily designed by directly mapping the graphical counter tree diagram (CTD) representation of the addition algorithm to SE devices and circuits. We propose two design approaches to implement fast adders using SE transfer circuits the threshold approach and the periodic approach. The periodic approach uses the voltage-controlled single-electron transfer characteristics to efficiently achieve periodic arithmetic functions. We use HSPICE simulator to verify fast adders operations. The speeds of the proposed adders are fast. The numbers of transistors of the adders are much smaller than conventional approaches. The power dissipations are much lower than CMOS and multiple-valued current-mode fast adders. (C) 2009 Elsevier Ltd. All rights reserved.

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We designed and fabricated a four-channel reconfigurable optical add-drop multiplexer based on silicon photonic wire waveguide, which is controlled through the thermo-optic effect. The effective footprint of the device is about 1000 x 500 mu m(2). The minimum insertion loss including the transmission loss and coupling loss is about 10.7 dB. The tuning bandwidth is about 17 nm, the average tuning efficiency about 6.11 mW/nm and the tuning speed about 24.5 kHz. (c) 2009 Elsevier B.V. All rights reserved.

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National Basic Research Programme of China G2009CB929300 National Natural Science Foundation of China 10404010 6052100160776061Supported by the National Basic Research Programme of China under Grant No G2009CB929300, and the National Natural Science Foundation of China under Grant Nos 10404010, 60521001 and 60776061.

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A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

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The hydrogen dilution profiling (HDP) technique has been developed to improve the quality and the crystalline uniformity in the growth direction of mu c-Si:H thin films prepared by hot-wire chemical-vapor deposition. The high H dilution in the initial growth stage reduces the amorphous transition layer from 30-50 to less than 10 nm. The uniformity of crystalline content X-c in the growth direction was much improved by the proper design of hydrogen dilution profiling which effectively controls the nonuniform transition region of Xc from 300 to less than 30 nm. Furthermore, the HDP approach restrains the formation of microvoids in mu c-Si: H thin films with a high Xc and enhances the compactness of the film. As a result the stability of mu c-Si: H thin films by HDP against the oxygen diffusion, as well as the electrical property, is much improved. (c) 2005 American Institute of Physics.

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A folding nonblocking 4 X 4 optical matrix switch in simplified-tree architecture was designed and fabricated on a silicon-on-insulator wafer. To compress chip size, switch elements (SEs) were connected by total internal reflection mirrors instead of conventional S-bends. For obtaining smooth interfaces, potassium hydroxide (KOH) anisotropic chemical etching of silicon was employed. The device has a compact size of 20 X 3.2 mm(2) and a fast response of 8 +/- 1 mu s. Power consumption of 2 x 2 SE and excess loss per mirror were 145 mW and -1.1 dB, respectively. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

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We propose an effective admittance ( EA) method to design antireflection structures for two-dimensional photonic crystals (PCs). We demonstrate that a compact and efficient antireflection structure, which is difficult to obtain by the conventional admittance matching method, can be readily designed by the EA method. The antireflection structure consists of an air slot resonant cavity that is constructed only with the materials that constitute the PC. Compared with a bare PC, the reflection from a PC with an antireflection structure is reduced by two orders of magnitude over a wide bandwidth. To confirm the presented EA method, finite-difference time-domain (FDTD) simulations are performed, and the results from the FDTD and the EA method are in good agreement.

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Using a low temperature grown GaAs wafer as an intracavity saturable absorber, a temporal envelope duration of 11 ns of Q- switched and mode- locked ( QML) 1064 nm operation was achieved in a very simple compact plane- concave cavity Nd: YVO4 laser, it was so short that the pulses can be used as Q- switching pulses. The maximal average output power is 808 mW with the repetition rate of 25 kHz, and the corresponding peak power and energy of a single Q- switched pulse was 2.94 kW and 32.3 mu J, respectively. The mode- locked pulse trains inside the Q- switched pulse envelope had a repetition rate of 800 MHz.