Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

40 Gbits/s all-optical clock recovery for degraded signals using an amplified feedback laser

All-optical clock recovery for the return-to-zero modulation format is demonstrated experimentally at 40 Gbits/s by using an amplified feedback laser. A 40 GHz optical clock with a root-mean-square (rms) timing jitter of 130 fs and a carrier-to-noise ratio of 42 dB is obtained. Also, a 40 GHz optical clock with timing jitter of 137 fs is directly recovered from pseudo-non-return-to-zero signals degraded by polarization-mode dispersion (PMD). No preprocessing stage to enhance the clock tone is used. The rms timing jitter of the recovered clock is investigated for different values of input power and for varying amounts of waveform distortion due to PMD.

Disentangling geomagnetic and precipitation signals in an 80-Kyr Chinese loess record of Be-10

IEECAS SKLLQG

Astronomical signals in different climate proxies from the quaternary loess-soil sequences in China

IEECAS SKLLQG

The time and energy signals, counter plateau, energy resolution and gas gains performances of a new kind of micro-pattern gaseous detector-Micromegas

In present paper, a new Micromegas detector is developed, and its time and energy signals are obtained in the figure form. The rising time of fast time signal is less than 2 ns due to the very fast collection of avalanche electrons, and the rising time of the energy pulse is about 100 ns, which is corresponding to the total collecting time of the electrons and ions in the avalanche process. The counter plateau, energy resolution and the gas gains of the detector have been compared with other groups' experimental results and the Garfield simulation result.