TWO-DIMENSIONAL ARRAY OF ION TRAPS ON A PLANAR CHIP

We investigate a planar ion chip design with a two-dimensional array of linear ion traps for the scalable quantum information processor. The segmented electrodes reside in a single plane on a substrate and a grounded metal plate, a combination of appropriate rf and DC potentials are applied to them for stable ion confinement, and the trap axes are located above the surface at a distance controlled by the electrodes' lateral extent and the substrate's height as discussed. The potential distributions are calculated using static electric field qualitatively. This architecture is conceptually simple and many current microfabrication techniques are feasible for the basic structure. It may provide a promising route for scalable quantum computers.

Improved uniformity of target illumination by combining a lens array and the technique of spectral dispersion

A scheme using a lens array and the technique of spectral dispersion is presented to improve target illumination uniformity in laser produced plasmas. Detailed two-dimensional simulation shows that a quasi-near-field target pattern, of steeper edges and without side lobes, is achieved with a lens array, while interference stripes inside the pattern are smoothed out by the use of the spectral dispersion technique. Moving the target slightly from the exact focal plane of the principal focusing lens can eliminate middle-scale-length intensity fluctuation further. Numerical results indicate that a well-irradiated laser spot with small nonuniformity and great energy efficiency can be obtained in this scheme. (c) 2007 American Institute of Physics.

Chromosome painting in the long-tailed field mouse provides insights into the ancestral murid karyotype

We report on the hybridization of mouse chromosomal paints to Apodemus sylvaticus, the long-tailed field mouse. The mouse paints detected 38 conserved segments in the Apodemus karyotype. Together with the species reported here there are now six species of rodents mapped with Mus musculus painting probes. A parsimony analysis indicated that the syntenies of nine M. musculus chromosomes were most likely already formed in the muroid ancestor: 3, 4, 7, 9, 14, 18, 19, X and Y. The widespread occurrence of syntenic segment associations of mouse chromosomes 1/17, 2/13, 7/19, 10/17, 11/16, 12/17 and 13/15 suggests that these associations were ancestral syntenies for muroid rodents. The muroid ancestral karyotype probably had a diploid number of about 2n = 54. It would be desirable to have a richer phylogenetic array of species before any final conclusions are drawn about the Muridae ancestral karyotype. The ancestral karyotype presented here should be considered as a working hypothesis. Copyright (C) 2004 S. Karger AG, Basel.

Fabrication and Characterization of High Power InGaN Blue-Violet Lasers with an Array Structure

InGaN/GaN multi-quantum-well-structure laser diodes with an array structure are successfully fabricated on sapphire substrates. The laser diode consists of four emitter stripes which share common electrodes on one laser chip. An 800-mu m-long cavity is formed by cleaving the substrate along the < 1 (1) over bar 00 >. orientation using laser scriber. The threshold current and voltage of the laser array diode are 2A and 10.5 V, respectively. A light output peak power of 12W under pulsed current injection at room temperature is achieved. We simulate the electric properties of GaN based laser diode in a co-planar structure and the results show that minimizing the difference of distances between the different ridges and the n-electrode and increasing the electrical conductivity of the n-type GaN are two effective ways to improve the uniformity of carrier distribution in emitter stripes. Two pairs of emitters on a chip are arranged to be located near the two n-electrode pads on the left and right sides, and the four stripe emitters can laser together. The laser diode shows two sharp peaks of light output at 408 and 409 nm above the threshold current. The full widths at half maximum for the parallel and perpendicular far field patterns are 8 degrees and 32 degrees, respectively.

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

A low-cost CMOS programmable temperature

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature T-th can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature T-th variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 mu m CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature T(th)s from 45-120 degrees C with a 5 degrees C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm(2) and power consumption is 3.1 mu A at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis.

Multiple valley couplings in nanometer Si metal-oxide-semiconductor field-effect transistors

We investigate the couplings between different energy band valleys in a metal-oxide-semiconductor field-effect transistor (MOSFET) device using self-consistent calculations of million-atom Schrodinger-Poisson equations. Atomistic empirical pseudopotentials are used to describe the device Hamiltonian and the underlying bulk band structure. The MOSFET device is under nonequilibrium condition with a source-drain bias up to 2 V and a gate potential close to the threshold potential. We find that all the intervalley couplings are small, with the coupling constants less than 3 meV. As a result, the system eigenstates derived from different bulk valleys can be calculated separately. This will significantly reduce the simulation time because the diagonalization of the Hamiltonian matrix scales as the third power of the total number of basis functions. (C) 2008 American Institute of Physics.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

Slow wave effect of 2-D photonic crystal coupled cavity array

We designed a two-dimensional coupled photonic crystal resonator array with hexagonal lattice. The calculation by plane-wave-expansion method shows that the dispersion curve of coupled cavity modes in the bandgap are much flattened in all directions in the reciprocal space. We simulated the transmission spectra of transverse electric (TE) wave along the Gamma K direction. Compared with the PC single cavity structure, the transmission ratio of the coupled cavity array increases more than three orders of magnitude, while the group velocity decreases to below 1/10, reaching 0.007c. The slow wave effect has potential application in the field of miniaturized tunable optical delay components and low-threshold photonic crystal lasers.

Electric field driven quantum phase transition between band insulator and topological insulator

We demonstrate theoretically that electric field can drive a quantum phase transition between band insulator to topological insulator in CdTe/HgCdTe/CdTe quantum wells. The numerical results suggest that the electric field could be used as a switch to turn on or off the topological insulator phase, and temperature can affect significantly the phase diagram for different gate voltage and compositions. Our theoretical results provide us an efficient way to manipulate the quantum phase of HgTe quantum wells.

A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

Dependence of elastic strain field on the self-organized ordering of quantum dot superlattices

A systematic investigation of the strain distribution of self-organized, lens-shaped quantum dot in the case of growth direction on (001) substrate was presented. The three-dimensional finite element analysis for an array of dots was used for the strain calculation. The dependence of the strain energy density distribution on the thickness of the capping layer was investigated in detail when the elastic characteristics of the matrix material were anisotropic. It is shown that the elastic anisotropic greatly influences the stress, strain, and strain energy density in the quantum dot structures. The anisotropic ratio of the matrix material and the combination with different thicknesses of the capping layer, may lead to different strain energy density minimum locations on the capping layer surface, which can result in various vertical ordering phenomena for the next layer of quantum dots, i.e. partial alignment, random alignment, and complete alignment.

Quantum mechanical effects in nanometer field effect transistors

The atomistic pseudopotential quantum mechanical calculations for million atom nanosized metal-oxide-semiconductor field-effect transistors (MOSFETs) are presented. When compared with semiclassical Thomas-Fermi simulation results, there are significant differences in I-V curve, electron threshold voltage, and gate capacitance. In many aspects, the quantum mechanical effects exacerbate the problems encountered during device minimization, and it also presents different mechanisms in controlling the behaviors of a nanometer device than the classical one. (c) 2007 American Institute of Physics.

Structure optimization of field-plate AlGaN/GaN HEMTs

AlGaN/GaN high electron mobility transistors (HEMTs) on 6H-SiC with varying field-plate length and gate-drain spacing were fabricated and analyzed. The classical small signal FET model and the well-known ColdFET method were used to extract the small signal parameters of the devices. Though the devices with field plates exhibited lower better f(T) characteristic, they did demonstrate better f(max), MSG and power density performances than the conventional devices without field plate. Besides, no independence of DC characteristic on field-plate length was observed. With the increase of the field-plate length and the gate-drain spacing, the characteristic of f(T) and f(max), degraded due to the large parasitic effects. Loadpull method was used to measure the microwave power performance of the devices. Under the condition of continuous wave at 5.4 GHz, an output power density of 4.69 W/mm was obtained for device with field-plate length of 0.5 mu m and gate-drain length of 2 mu m. (c) 2006 Elsevier Ltd. All rights reserved.

Growth and characterization of 0.8-mu m gate length AlGaN/GaN HEMTs on sapphire substrates

AlGaN/GaN high electron mobility transistor (HEMT) structures were grown on 2 inch sapphire substrates by MOCVD, and 0.8-mu m gate length devices were fabricated and measured. It is shown by resistance mapping that the HEMT structures have an average sheet resistance of approximately 380 Omega/sq with a uniformity of more than 96%. The 1-mm gate width devices using the materials yielded a pulsed drain current of 784 mA/mm at V-gs=0.5 V and V-ds=7 V with an extrinsic transconductance of 200 mS/mm. A 20-GHz unity current gain cutoff frequency (f(T)) and a 28-GHz maximum oscillation frequency (f(max)) were obtained. The device with a 0.6-mm gate width yielded a total output power of 2.0 W/mm (power density of 3.33 W/mm) with 41% power added efficiency (PAE) at 4 GHz.