垂直结构金属基极有机晶体管及其在有机发光驱动中的应用

近几十年来，有机半导体材料作为新一代的信息功能材料正以其光电性能优异、生产成本低廉、加工工艺简单、选材范围宽广、机械性能柔软等显著的优点，吸引了世界范围内的目光，成为越来越多研究机构竞相研究和开发的对象，被广泛应用于发光二极管、薄膜晶体管、太阳能电池、存储器等光电子器件中。这些有机半导体器件的应用前景十分广阔，其巨大的商业价值极大地推动了有机半导体器件的发展。 本论文主要制备了N型金属基极有机晶体管，并对其性能进行了研究和分析，并在此基础上，研究了其在有机发光驱动中的应用。 (1) 用N型有机半导体材料Alq3、F16CuPc和BAlq3作发射极层，Au作为基极，N型硅作为收集极层，Al作为发射极接触电极成功地制备出了一系列N型无机/有机杂化金属基极晶体管，这些器件都表现出了良好的共基极增益特性，最大共基极增益达到了0.991，接近理想值1。在此基础上，通过在发射极层和发射极电极之间引入V2O5界面修饰层，还实现了具有良好共发射极特性的N型无机/有机杂化金属基极晶体管。研究发现，V2O5界面修饰层的引入明显地减小了共基极漏电流，使器件的共基极特性得到了进一步的改善，同时也使器件表现了共发射极特性，实现了电流的放大，我们已经把共基极特性的改善和共发射极特性的实现归功于界面修饰层的引入提高了电子注入的结果。 (2) 根据金属与半导体的接触理论,设计制备出了带有Au/Al双层金属基极的N型无机/有机杂化金属基极晶体管。由于Al和Alq3之间好的接触特性和有效的从Al到Alq3的空穴阻挡特性以及Au和Si之间良好的肖特基接触特性，大大降低了器件的漏电流，使器件在低的电压下表现了优异的共基极和共发射极特性，共基极增益达到了近似理想值1，最大共发射机增益达到了4000，克服了单层金属基极晶体管难实现共发射极特性的问题，为实现高性能金属基极晶体管提供了新的思路。 (3) 利用异质结的概念，设计制备出了带有BAlq3/Alq3异质结结构的N型无机/有机杂化金属基极晶体管，该器件同样表现了优异的共基极和共发射极特性。研究发现，同Alq3单发射极层结构的金属基极晶体管相比，BAlq3/Alq3异质结发射极层的使用进一步降低了器件的漏电流，使器件在相同的电压下表现了更高的输出电流和更高的共发射极增益，为进一步实现高性能金属基极晶体管提供了新的方法。 (4) 用有机半导体材料取代无机高掺杂硅作为收集极层，制备出了带有Al单层金属基极和Au/Al双层金属基极的N型垂直结构全有机金属基极晶体管，该器件表现出了良好的共基极特性和共发射极特性。研究表明，全有机金属基极晶体管表现了和无机/有机混合型金属基极晶体管相似的特性，其从本质上说也是一种渗透型金属基极晶体管。 (5) 实现了金属基极有机晶体管驱动有机发光二极管的集成器件。利用金属基极有机晶体管的共发射极电流放大特性，在基极输入电流IB量级比较低（uA）的情况下，得到了较大量级（mA）的输出电流IC，从而实现了对白光有机发光二极管的驱动，在基极输入电流IB为1×10-5A时有机发光二极管的亮度达到了1279 cd/m2。

INTERFACIAL REACTIONS IN THE CO/SI/GAAS AND SI/CO/GAAS SYSTEMS

The interfacial reactions between thin films of cobalt and silicon and (100)-oriented GaAs substrates in two configurations, Co/Si/GaAs and Si/Co/GaAs, were studied using a variety of techniques including Auger electron spectroscopy, x-ray diffraction, and transmission electron microscopy. The annealing conditions were 200, 300, 400, 600-degrees-C for 30 min, and rapid thermal annealing for 15 s. It was found that Si layer in the Co/Si/GaAs system acts as a barrier at the interface between Co and GaAs when annealed up to 600-degrees-C. The interfacial reaction between Co and Si is faster than that between Co and GaAs in the system of Si/Co/GaAs. The sequence of compound formation for the two metallizations studied (Co/Si/GaAs and Si/Co/GaAs) depends strongly on the sample configuration as well as the layer thickness of Si and Co (Co/Si atomic ratio). From our results, it is promising to utilize Co/Si/GaAs multilayer film structure to make a CoSi2/GaAs contact, and this CoSi2 may offer an alternative to the commonly used W silicides as improved gate metallurgies in self-aligned metal-semiconductor field effect transistor (MESFET) technologies.

Role of the evanescent states in the electron transport in quantum waveguides

Recognizing the computational difficulty due to the exponential behavior of the evanescent states in the calculations of the electron transmission in waveguide structures, the authors propose two transfer matrix methods and apply them to investigate the influence of the evanescent states on the electron wave propagation. The study shows that the effect of the evanescent states on the electron transport is obvious when the electron energy is close to the subband minima. The results show that the calculated transmissions are much enhanced if the evanescent states are omitted in the calculations. For the multiple-stub structures, it is found that the connecting channel length has a critical effect on the electron transmission depending on it larger or smaller than the attenuation lengths of evanescent states. Based on the study of the evanescent states, a new kind of waveguide structures which exhibit quantum modulated transistor action is proposed. (C) 1997 American Institute of Physics.

硅基光波导化学传感器研究

研究了基于硅基集成光波导的马赫-曾德干涉仪(MZI)型化学传感芯片的设计、制备及相关敏感特性的模拟和分析.传感芯片采用硅基二氧化硅光波导材料,利用与传统互补型金属氧化物半导体(CMOS)兼容的工艺技术制作.通过波导的单模设计以及对MZI结构的优化,获得了有效折射率分辨率达到10~(-7)量级的高灵敏度传感芯片.作为化学传感器,把MZI的其中一臂设计成传感臂.并进行适当的表面修饰,可制作出高灵敏度的干涉型光波导化学传感器.最后,对该传感器的折射率分辨率、敏感特性等进行了分析、模拟,同时,对面临的关键问题进行了分析和讨论.

A voltage-controlled ring oscillator using InP full enhancement-mode HEMT logic

A voltage-controlled ring oscillator (VCO) based on a full enhancement-mode InAIAs/InGaAs/InP high electron mobility transistor (HEMT) logic is proposed. An enhancement-mode HEMT (E-HEMT) is fabricated, whose threshold is demonstrated to be 10 mV. The model of the E-HEMT is established and used in the SPICE simulation of the VCO. The result proves that the full E-HEMT logic technology can be applied to the VCO. And compared with the HEMT DCFL technology, the complexity of our fabrication process is reduced and the reliability is improved.

片上集成自动可调谐非对称带通滤波器

提出了具有3阶高通、2阶低通的带有自动调谐系统的有源电阻电容非对称带通滤波器结构.带通滤波器的中心频率为4.055 MHz,带宽为2.63 MHz.源阻抗为50Ω时,滤波器带内3阶交凋量为18.489 dB·m.滤波器输人参考噪声为47.91×10~(-6)V_(rms)(均方根电压).滤波器采用基于二进制搜索算法(BSA)的调谐方案,其调谐精度为(-1.65%,2.66%).调谐电路的芯片面积为0.282 mm×0.204 mm,不到主滤波器面积的1/5.调谐系统完成调谐功能后会自动关闭,降低了功耗和对主滤波器的串扰.在1.8 V电源电压下,滤波器消耗电流为1.96 mA.该滤波器已在IBM 0.18 μm标准互补金属氧化物半导体(CMOS)工艺线流片成功.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

一种带有精准调谐结构的有源RC低通滤波器的设计

提出了一种带有精准调谐结构的有源RC低通滤波器的设计方案,其截止频率为5MHz,并在0.18μm标准CMOS工艺线上流片得到验证.调谐精度达到(-1.24%,+2.16%),测试中得到验证.调谐系统所占芯片面积仅为主滤波器面积的1/4.调谐系统完成调谐功能后会自动关闭,降低了功耗以及对主滤波器的串扰.以50Ω作为源阻抗,滤波器带内3阶交调量(IIP3)好于16.1dBm.滤波器输入参考噪声为36μVrms.滤波器群延迟时间波动测试结果为24ns.滤波器功耗为3.6mW.带有这种调谐结构的滤波器容易被实现,可以用于很多无线低中频应用中,例如全球定位系统、全球通和码分多址等芯片系统中.

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

A High Performance AlGaN/GaN HEMT with a New Method for T-Gate Layout Design

We propose and fabricate an A1GaN/GaN high electron mobility transistor （HEMT） on sapphire substrate using a new kind of electron beam （EB） lithography layout for the T-gate. Using this new layout,we can change the aspect ratio （ratio of top gate dimension to gate length） and modify the shape of the T-gate freely. Therefore, we obtain a 0.18μm gate-length AlGaN/GaN HEMT with a unity current gain cutoff frequency （f_T） of 65GHz. The aspect ratio of the T-gate is 10. These single finger devices also exhibit a peak extrinsic transconductance of 287mS/mm and a maximum drain current as high as 980mA/mm.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD, we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.