Effect of channel surface wettability and temperature gradients on the boiling flow pattern in a single microchannel

The objective of this paper is to investigate the effects of channel surface wettability and temperature gradients on the boiling flow pattern in a single microchannel. The test section consists of a bottom silicon substrate bonded with a top glass cover. Three consecutive parts of an inlet fluid plenum, a central microchannel and an outlet fluid plenum were etched in the silicon substrate. The central microchannel had a width of 800 mu m and a depth of 30 mu m. Acetone liquid was used as the working fluid. High outlet vapor qualities were dealt with here. The flow pattern consists of a fluid triangle (shrinkage of the liquid films) and a connected long liquid rivulet, which is generated in the central microchannel in the timescale of milliseconds. The peculiar flow pattern is formed due to the following reasons: (1) the liquid rivulet tends to have a large contact area with the top hydrophilic channel surface of the glass cover, but a smaller contact area with the bottom silicon hydrophobic surface. (2) The temperature gradient in the chip width direction at the top channel surface of the glass cover not only causes the shrinkage of the liquid films in the central microchannel upstream, but also attracts the liquid rivulet populated near the microchannel centerline. (3) The zigzag pattern is formed due to the competition between the evaporation momentum forces at the vapor-liquid interfaces and the force due to the Marangoni effect. The former causes the rivulet to deviate from the channel centerline and the latter draws the rivulet toward the channel centerline. (4) The temperature gradient along the flow direction in the central microchannel downstream causes the breakup of the rivulet to form isolated droplets there. (5) Liquid stripes inside the upstream fluid triangle were caused by the small capillary number of the liquid film, at which the large surface tension force relative to the viscous force tends to populate the liquid film locally on the top glass cover surface.

The design and operation of a new clapboard-type internal circulating fluidized-bed gasifier

The design and operation of a new clapboard-type internal circulating fluidized-bed gasifier is proposed in this article. By arranging the clapboard in the bed, the gasifier is thus divided into two regions, which are characterized by different fluidization velocities. The bed structure is designed so that it can guide the circulating flow passing through the two regions, and therefore the feedstock particles entrained in the flow experience longer residence time. The experimental results based on the present new design, operating in the temperature range of 790 degrees C-850 degrees C, indicate that the gas yield is from 1.6-1.9 Nm(3)/kg feedstock, the gas enthalpies are 5,345 kJ/Nm(3) for wood chip and 4,875 kJ/m(3) for rice husk, and a gasification efficiency up to 75% can be obtained.

Numerical simulations of interrupted and conventional microchannel heat sinks

We provide three-dimensional numerical simulations of conjugate heat transfer in conventional and the newly proposed interrupted microchannel heat sinks. The new microchannel heat sink consists of a set of separated zones adjoining shortened parallel microchannels and transverse microchambers. Multi-channel effect, physical property variations, and axial thermal conduction are considered. It is found that flow rate variations in different channels can be neglected, while heat received by different channels accounts for 2% deviations from the averaged value when the heat flux at the back surface of the silicon chip reaches 100 W/cm(2). The computed hydraulic and thermal boundary layers are redeveloping in each separated zone due to shortened flow length for the interrupted microchannel heat sink. The periodic thermal developing flow is responsible for the significant heat transfer enhancement. Two effects influence pressure drops across the newly proposed microchannel heat sink. The first one is the pressure recovery effect in the microchamber, while the second one is the head loss when liquid leaves the microchamber and enters the next zone. The first effect compensates or suppresses the second one, leading to similar or decreased pressure drop than that for the conventional microchannel heat sink, with the fluid Prandtl number larger than unity.

Continuous-flow polymerase chain reaction microfluidics by using spiral capillary channel embedded on copper

This paper presents a novel method for performing polymerase chain reaction (PCR) amplification by using spiral channel fabricated on copper where a transparent polytetrafluoroethylene ( PTFE) capillary tube was embedded. The channel with 25 PCR cycles was gradually developed in a spiral manner from inner to outer. The durations of PCR mixture at the denaturation, annealing and extension zones were gradually lengthened at a given flow rate, which may benefit continuous-flow PCR amplification as the synthesis ability of the Taq polymerase enzyme usually weakens with PCR time. Successful continuous-flow amplification of DNA fragments has been demonstrated. The PCR products of 249, 500 and 982 bp fragments could be obviously observed when the flow rates of PCR mixture were 7.5, 7.5 and 3.0 mm s(-1), respectively, and the required amplification times were about 25, 25, and 62 min, respectively. Besides, the successful segmented-flow PCR of three samples ( 249, 500 and 982 bp) has also been reported, which demonstrates the present continuous-flow PCR microfluidics can be developed for high-throughput genetic analysis.

Transient flow patterns and bubble slug lengths in parallel microchannels with oxygen gas bubbles produced by catalytic chemical reactions

Transient flow patterns and bubble slug lengths were investigated with oxygen gas (O-2) bubbles produced by catalytic chemical reactions using a high speed camera bonded with a microscope. The microreactor consists of an inlet liquid plenum, nine parallel rectangular microchannels followed by a micronozzle, using the MEMS fabrication technique. The etched surface was deposited by the thin platinum film, which is acted as the catalyst. Experiments were performed with the inlet mass concentration of the hydrogen peroxide from 50% to 90% and the pressure drop across the silicon chip from 2.5 to 20.0 kPa. The silicon chip is directly exposed in the environment thus the heat released via the catalytic chemical reactions is dissipated into the environment and the experiment was performed at the room temperature level. It is found that the two-phase flow with the catalytic chemical reactions display the cyclic behavior. A full cycle consists of a short fresh liquid refilling stage, a liquid decomposition stage followed by the bubble slug flow stage. At the beginning of the bubble slug flow stage, the liquid slug number reaches maximum, while at the end of the bubble slug flow stage the liquid slugs are quickly flushed out of the microchannels. Two or three large bubbles are observed in the inlet liquid plenum, affecting the two-phase distributions in microchannels. The bubble slug lengths, cycle periods as well as the mass flow rates are analyzed with different mass concentrations of hydrogen peroxide and pressure drops. The bubble slug length is helpful for the selection of the future microreactor length ensuring the complete hydrogen peroxide decomposition. Future studies on the temperature effect on the transient two-phase flow with chemical reactions are recommended.

Real-time data processing of interferential imaging spectrometer based on FPGA

Based on the data processing technologies of interferential spectrometer, a sort of real-time data processing system on chip of interferential imaging spectrometer was studied based on large capacitance and high speed field programmable gate array( FPGA) device. The system integrates both interferograrn sampling and spectrum rebuilding on a single chip of FPGA and makes them being accomplished in real-time with advantages such as small cubage, fast speed and high reliability. It establishes a good technical foundation in the applications of imaging spectrometer on target detection and recognition in real-time.

1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS tech nology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capaci tance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resis tance is 50 Ω, and the average input noise current spectral density is 9.7 pA/(Hz)~(1/2). Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz~(1/2) input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f_0 = 20 MHz) from 5 V supply, and occupy 0.5 mm~2.

面向硅基光互连应用的无源光子集成器件研究进展

光互连是突破传统微电子IC性能瓶颈的重要技术手段,对推进"后摩尔时代"微电子技术的发展和高性能计算技术的实现具有关键性意义.本文在归纳总结不同层次光互连结构特点的基础上,对片上光互连(on-chip or intra-chip optical interconnects)所涉及的若干种无源光子集成器件的设计制备及性能特点进行了分析介绍,这些器件包括SOI亚波长光子线波导、SOI光子晶体波导、MMI分束/合束器、微环/微盘谐振腔滤波器、光子晶体微腔耦合滤波器、光子晶体反射镜等,是硅基片上光互连的基本构成单元.本文对这些关键性光子集成器件的国内最新研究进展进行了报道.

A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver

This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process. With a high Q on-chip inductor, the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage. Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than - 82dBc/Hz and out-of-band phase noise about - ll2dBc/Hz at 1MHz offset from a 3. 142GHz carrier. The performance of the frequency synthesizer meets the requirements of GPS applications very well.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD, we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.

A Novel Power Supply Solution of a Passive RFID Transponder

This paper presents a power supply solution for fully integrated passive radio-frequency identification(RFID) transponder IC,which has been implemented in 0.35μm CMOS technology with embedded EEPROM from Chartered Semiconductor.The proposed AC/DC and DC/DC charge pumps can generate stable output for RFID applications with quite low power dissipation and extremely high pumping efficiency.An analytical model of the voltage multiplier,comparison with other charge pumps,simulation results,and chip testing results are presented.