High Temperature Characteristics of 3C-SiC/Si Heterojunction Diodes Grown by LPCVD

The high temperature (300～480K) characteristics of the n-3C-SiC/p-Si heterojunction diodes (HJD) fabricated by low-pressure chemical vapor deposition on Si (100) substrates are investigated.The obtained diode with best rectifying properties has 1.8×104 of ratio at room temperature,and slightly rectifying characteristics with 3.1 of rectification ratio is measured at 480K of an ambient temperature .220V of reverse breakdown voltage is acquired at 300K.Capacitance-voltage characteristics show that the abrupt junction model is applicable to the SiC/Si HJD structure and the built-in voltage is 0.75V.An ingenious equation is employed to perfectly simulate and explain the forward current density-voltage data measured at various temperatures.The 3C-SiC/Si HJD represents a promising approach for the fabrication of high quality heterojunction devices such as SiC-emitter heterojunction bipolar transistors.

Heteroepitaxial Growth and Heterojunction Characteristics of Voids-Free n-3C-SiC on p-Si(100)

Highly oriented voids-free 3C-SiC heteroepitaxial layers are grown on φ50mm Si (100) substrates by low pressure chemical vapor deposition (LPCVD). The initial stage of carbonization and the surface morphology of carbonization layers of Si(100) are studied using reflection high energy electron diffraction (RHEED) and scanning electron microscopy (SEM). It is shown that the optimized carbonization temperature for the growth of voids-free 3S-SiC on Si (100) substrates is 1100 ℃. The electrical properties of SiC layers are characterized using Van der Pauw method. The I-V, C-V, and the temperature dependence of I-V characteristics in n-3C-SiC-p-Si heterojunctions with AuGeNi and Al electrical pads are investigated. It is shown that the maximum reverse breakdown voltage of the n-3C-SiC-p-Si heterojunction diodes reaches to 220V at room temperature. These results indicate that the SiC/Si heterojunction diode can be used to fabricate the wide bandgap emitter SiC/Si heterojunction bipolar transistors (HBT's).

分子束外延生长赝配高电子迁移率超高速微结构功能材料里深中心识别

应用深能级瞬态谱（DLTS）技术研究分子束外延（MBE）生长的high electron mobility transistors （HEMT）和Pseudomorphic high electron mobility transistors （P-HEMT）结构深中心行为。样品的DLTS谱表明，在HEMT和P-HEMT结构的n-AlGaAs层里存在着较大浓度（10~(15)-10~(17)cm~(-3)）和俘获截面（10~(-16)cm~2）的近禁带中部电子争阱。它们可能与AlGaAs层的氧含量有关。同时还观察到P-HEMT结构晶格不匹配的AlGaAs/InGaAs/GaAs系统在AlGaAs里产生的应力引起DX中心（与硅有关）能级位置的有序移动。其移动量可作为应力大小的一个判据，表明DLTS技术是定性识别此应力的可靠和简便的工具。

Effects of polarization field on formation of two-dimensional electron gas in (0001) and (11(2)over-bar0) plane AlGaN/GaN heterostructures

Photoluminescence (PL) and temperature-dependent Hall effect measurements were carried out in (0001) and (11 (2) over bar0) AlGaN/GaN heterostructures grown on sapphire substrates by metalorganic chemical vapor deposition. There are strong spontaneous and piezoelectric electric fields (SPF) along the growth orientation of the (0001) AlGaN/GaN heterostructures. At the same time there are no corresponding SPF along that of the (1120) AlGaN/GaN. A strong PL peak related to the recombination between two-dimensional electron gas (2DEG) and photoexcited holes was observed at 3.258 eV at room temperature in (0001) AlGaN/GaN heterointerfaces while no corresponding PL peak was observed in (11 (2) over bar0). The existence of a 2DEG was observed in (0001) AlGaN/GaN multi-layers with a mobility saturated at 6000 cm(2)/V s below 80 K, whereas a much lower mobility was measured in (11 (2) over bar0). These results indicated that the SPF was the main element to cause the high mobility and high sheet-electron-density 2DEG in AlGaN/GaN heterostructures. (C) 2004 Elsevier B.V. All rights reserved.

Space-grown SI-GaAs and its application

A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-travelling furnace under microgravity. The crystal was characterized systematically and was used in fabricating low noise field effect transistors and analogue switch integrated circuits by the direct ion-implantation technique. All key electrical properties of these transistors and integrated circuits have surpassed those made from conventional earth-grown gallium arsenide. This result shows that device-grade space-grown semiconducting single. crystal has surpassed the best. terrestrial counterparts. Studies on the correlation between SI-GaAs wafers and the electronic devices and integrated circuits indicate that the characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry.

Structural properties of polycrystalline silicon films formed by pulsed rapid thermal processing

A novel pulsed rapid thermal processing (PRTP) method has been used for realizing the solid-phase crystallization of amorphous silicon films prepared by PECVD. The microstructure and surface morphology of the crystallized films are investigated by X-ray diffraction (XRD) and atomic force microscopy (AFM). The results indicate that this PRTP is a suitable post-crystallization technique for fabricating large-area polycrystalline silicon films with good structural qualities such as large grain size, small lattice microstain and smooth surface morphology on low-cost substrate.

JFET SOS devices: Processing and gamma radiation effects

A process for fabricating n channel JFET/SOS (junction field-effect transistors on silicon-on-sapphire) has been researched. The gate p(+)n junction was obtained by diffusion, and the conductive channel was gotten by a double ion implantation. Both enhancement and depletion mode transistors were fabricated in different processing conditions. From the results of the Co-50 gamma ray irradiation experimental we found that the devices had a good total dose radiation-hardness. When the tot;ll dose was 5Mrad(Si), their threshold voltages shift was less than 0.1V. The variation of transconductance and the channel leakage current were also little.

Space grown semi-insulating gallium arsenide single crystal and its application

Low noise field effect transistors and analogue switch integrated circuits (ICs) have been fabricated in semi-insulating gallium arsenide (SI-GaAs) wafers grown in space by direct ion-implantation. The electrical behaviors of the devices and the ICs have surpassed those fabricated in the terrestrially grown SI-GaAs wafers. The highest gain and the lowest noise of the transistors made from space-grown SI-GaAs wafers are 22.8 dB and 0.78 dB, respectively. The threshold back-gating voltage of the ICs made from space-grown SI-GaAs wafers is better than 8.5 V The con-elation between the characterizations of materials and devices is studied systematically. (C) 2002 COSPAR. Published by Elsevier Science Ltd. All rights reserved.

High-quality metamorphic HEMT grown on GaAs substrates by MBE

Metamorphic high electron mobility transistor (M-HEMT) structures have been grown on GaAs substrates by molecular beam epitaxy (MBE). Linearly graded and the step-graded InGaAs and InAlAs buffet layers hal e been compared, and TEM, PL and low-temperature Hall have been used to analyze the properties of the buffer layers and the M-HEMT structure. For a single-delta-doped M-HEMT structure with an In0.53Ga0.47As channel layer and a 0.8 mum step-graded InAlAs buffer layer, room-temperature mobility of 9000 cm(2)/V s and a sheet electron density as high as 3.6 x 10(12)/cm(2) are obtained. These results are nearly equivalent to those obtained for the same structure grown on an InP substrate. A basic M-HEMT device with 1 mum gate was fabricated, and g(m) is larger than 400 mS/mm. (C) 2001 Elsevier Science B.V. All rights reserved.

Semi-insulating GaAs grown in outer space

A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-traveling furnace under microgravity. The characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry, i.e. the ration of two types of atoms in the crystal. a practical technique for nondestructive and quantitative measuring stoichiometry in GaAs single crystal was used to analyze the space-grown GaAs single crystal. The distribution of stoichiometry in a GaAs wafer was measured for the first time. The electrical, optical and structural properties of the space-grown GaAs crystal were studied systematically, Device fabricating experiments prove that the quality of field effect transistors fabricated from direct ion-implantation in semi-insulating GaAs wafers has a close correlation with the crystal's stoichiometry. (C) 2000 Elsevier Science S.A. All rights reserved.

Behavior of Pentacene Initial Nucleation on Various Dielectrics and Its Effect on Carrier Transport in Organic Field-Effect Transistor

The influence of dielectric surface energy on the initial nucleation and the growth of pentacene films as well as the electrical properties of the pentacene-based field-effect transistors are investigated. We have examined a range of organic and inorganic dielectrics with different surface energies, such as polycarbonate/SiO2, polystyrene/SiO2, and PMMA/SiO2 bi-layered dielectrics and also the bare SiO2 dielectric. Atomic force microscopy measurements of sub-monolayer and thick pentacene films indicated that the growth of pentacene film was in Stranski-Kranstanow growth mode on all the dielectrics. However, the initial nucleation density and the size of the first-layered pentacene islands deposited on different dielectrics are drastically influenced by the dielectric surface energy. With the increasing of the surface energy, the nucleation density increased and thus the average size of pentacene islands for the first mono-layer deposition decreased. The performance of fabricated pentacene-based thin film transistors was found to be highly related to nucleation density and the island size of deposited Pentacene film, and it had no relationship to the final particle size of the thick pentacene film. The field effect mobility of the thin film transistor could be achieved as high as 1.38 cm(2)/Vs with on/off ratio over 3 x 10(7) on the PS/SiO2 where the lowest surface energy existed among all the dielectrics. For comparison, the values of mobility and on/off ratio were 0.42 cm(2)/Vs and 1 x 10(6) for thin film transistor deposited directly on bare SiO2 having the highest surface energy.

Experimental study on heavy ion single event effects in SOI SRAMs

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened military and space applications. The use of SOI has been motivated by the full dielectric isolation of individual transistors, which prevents latch-up. The sensitive region for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single event upset (SEU). In this study, 64 kB SOI SRAMs were exposed to different heavy ions, such as Cu, Br, I, Kr. Experimental results show that the heavy ion SEU threshold linear energy transfer (LET) in the 64 kB SOI SRAMs is about 71.8 MeV cm(2)/mg. Accorded to the experimental results, the single event upset rate (SEUR) in space orbits were calculated and they are at the order of 10(-13) upset/(day bit).

A low noise charge sensitive preamplifier with switch control feedback resistance

In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94 Omega and the linearity almost good.

Hybrid metal-base transistor with base of sulfonated polyaniline and fullerene emitter

We demonstrate hybrid vertical architecture transistors that operate like metal-base transistors, using n-type silicon as the collector, sulfonated polyaniline as the base, and C-60 fullerene as the emitter. Electrical measurements suggest that the sulfonated polyaniline base effectively screens the emitter from electric field variations occurring in the collector leading to the metal-base transistor behavior.

The first soluble conjugated poly(2,6-anthrylene): synthesis and properties

The first soluble conjugated poly(2,6-anthrylene) with 9,10-diphenyl-anthracene as the repeating unit is reported; photophysical studies reveal that this polymer represents a novel well-conjugated system.